checks (tscircuit)ECADConfidence: Medium

getHoleGeometries only looks at pcb_hole, so via-to-track clearance is never checked. A 22-via board passes G0 through G3 while breaking JLCPCB's 0.2 mm rule.

Impact Analysis

Persona

Electrical Engineer

Team Size Impact

5x Multiplier

Prototype Delay

3 Days

Est. Annual Cost

$30,000

1 user · 1 month240 min
Rest of team960 min
Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources

tscircuit/checks Issue #501: [BUG] getHoleGeometries ignores pcb_via - checkHoleTraceClearance blind to via-track violations

github.com

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Analyst Notes

From the Grok pain-radar digests, Oct 31-Nov 1 2026 (Oct 31 9:41 PM ET through Nov 1 7:41 AM ET digests plus the Haitch overnight edition). Verified live 2026-11-01: issue/PR read; title and state confirmed.