Building a native EasyEDA Pro schematic for a 61-part power board from a golden netlist, the golden netlist names a FET's pins G/S/D, but the real SON/TDSON packages have 8 to 9 pads. A schematic that wires the S pin leaves pads 1 and 2 floating and still exports a netlist that matches the golden one, so the defect only appears in copper. The authors pulled pin-to-pad maps from a measured pin dump of the real devices and wrote a pad-level diff, plus a test that breaks a correct export eight ways so the ok: True is not self-certifying. Issue #9 says plainly that a PDF or screenshot cannot stand in for the CAD file.