Order-readiness pass on a 6-layer RF board and a 4-layer shack interface, with a script reading back layers, outline and holes from the fab files. The finding is that gen_rfboard_pcb.py no longer reproduces the RF board. A full run moves the A1_BIAS drain vias and gives 3 DRC errors, so the note is not to run it. The source script and the board drifted apart. DFM upload and RF routing sign-off are still open.