The lab's JLC capabilities file sets a 4 mil clearance floor for 4-layer 2 oz boards. A reviewer read JLC's page the same day as 0.15 mm for 2 oz multilayer. The hc-power board had 249 different-net outer track pairs below 0.15 mm, down to about 0.12 mm, and both DRC and the DFM gate were clean. Every 2 oz multilayer row shares the same value, so other boards inherit the mistake. The workaround is a hand-added spacing rule in the board's .kicad_dru, and the author notes the rules generator would overwrite it. The annular ring figure on the same page is also unconfirmed.