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Silinx-ISE (pmnmalo)ECADConfidence: Medium

A schematic bus tap on bits 5..5 of a 4-bit bus raises no diagnostic, while the generated HDL only warns, VHDL simulation stops, and Verilog gives x.

Impact Analysis

Persona
Electrical Engineer
Team Size Impact
5x Multiplier
Prototype Delay
3 Days
Est. Annual Cost
$30,000
  • 1 user · 1 month240 min
  • Rest of team960 min
  • Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources
pmnmalo/Silinx-ISE Issue #1690: Schematic: a bus tap of bits outside its bus is not reported (the generated HDL fails at simulation)
github.com
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Analyst Notes

From the Grok pain-radar digests, Oct 27-28 2026 (Oct 27 8:41 AM ET through Oct 28 7:41 AM ET digests plus the Haitch editions). Verified live 2026-10-28: issue/PR/thread read; title and state confirmed.