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simten (simtenHQ)ECADConfidence: Medium

Built-in Verilog mappings are matched by name, so a user's own primitive called Adder exports as the standard Adder's logic. The Verilog is wrong and nothing reports it (both API and editor Export button).

Impact Analysis

Persona
Electrical Engineer
Team Size Impact
5x Multiplier
Prototype Delay
3 Days
Est. Annual Cost
$30,000
  • 1 user · 1 month240 min
  • Rest of team960 min
  • Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources
simtenHQ/simten Issue #487: Verilog export: hand-written mappings apply by name, so a user's own Adder exports as std's
github.com
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Analyst Notes

From the Grok pain-radar digests, Oct 26-27 2026 (Oct 26 12:41 PM ET through Oct 27 7:41 AM ET digests plus the Haitch editions). Verified live 2026-10-27: issue/PR/thread read; title and state confirmed.