synth (absmach)ECADConfidence: Medium

In a board generator, the router and project file use JLCPCB's 0.56 mm minimum via but the board setup hardcodes 0.60 mm, so kicad-cli DRC throws blocking errors on vias that are legal at the fab.

Impact Analysis

Persona

Electrical Engineer

Team Size Impact

5x Multiplier

Prototype Delay

3 Days

Est. Annual Cost

$30,000

1 user · 1 month240 min
Rest of team960 min
Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources

absmach/synth Issue #315: Bug: the board file fixes the minimum via at 0.60 mm, so a legal 0.56 mm via fails DRC

github.com

→

Analyst Notes

From the Grok pain-radar digest, Oct 25-26 2026 (Oct 25 daytime to Oct 26 morning slots). Verified live 2026-10-26: issue/PR read on GitHub; title and state confirmed.