xeda (XedaHQ)ECADConfidence: Medium

The yosys STA pass rewrote the netlist it was only meant to analyze, and leftover assert and display cells stopped Vivado opt_design with DRC INBB-3 black-box errors.

Impact Analysis

Persona

Electrical Engineer

Team Size Impact

5x Multiplier

Prototype Delay

3 Days

Est. Annual Cost

$30,000

1 user · 1 month240 min
Rest of team960 min
Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources

XedaHQ/xeda PR #283: Fix the yosys_fpga netlists for sta and assertions, add out_of_context, and correct the skill

github.com

→

Analyst Notes

From the Grok pain-radar digests, Oct 26-27 2026 (Oct 26 12:41 PM ET through Oct 27 7:41 AM ET digests plus the Haitch editions). Verified live 2026-10-27: issue/PR/thread read; title and state confirmed.