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Silinx-ISE (pmnmalo)FirmwareConfidence: Medium

Changing the project's preferred HDL from VHDL to Verilog saves the setting, but every schematic and state diagram keeps generating its old .vhd file.

Impact Analysis

Persona
Firmware Engineer
Team Size Impact
5x Multiplier
Prototype Delay
3 Days
Est. Annual Cost
$30,000
  • 1 user · 1 month240 min
  • Rest of team960 min
  • Rest of year13,200 min

monthly_minutes × 12 × team_multiplier ÷ 60 × $75/hr = $30k/yr

$75/hr assumed rate.

Annual team-minutes decomposed from the reported monthly inputs.

Evidence & Sources

1 Sources
pmnmalo/Silinx-ISE Issue #1477: Design Properties: changing the Preferred Language leaves the drawings' HDL in the old language
github.com
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Analyst Notes

From the Grok pain-radar digest, Oct 25-26 2026 (Oct 25 daytime to Oct 26 morning slots). Verified live 2026-10-26: issue/PR read on GitHub; title and state confirmed.