An open-PDK PLL run by an agent fleet. With the prescaler at 5.0 GHz, "FB and MC never toggle over 120 ns." Alone, the divider gives 3 FB edges at 500 MHz and 0 at 625 MHz, which is exactly the prescaler output. The existing divider bench "only counted at 100 MHz ('Not covered: speed'), so nothing caught this." Four spec rows can't close with the real chain, and the loop sim uses a behavioural stand-in. PR #65 adds the 625 and 687.5 MHz check and records the bisect but does not fix the divider. A verification record that honestly said "not covered" still let the design move forward.