A new logic-equivalence gate proving RTL equals the synth netlist equals the final netlist, run plainly, abstracts the clock with eqy, and on a small fixture it passed a wrong clock edge, a set flop in place of a reset flop, and a flop with no reset at all. A stray gate planted in the final netlist passed gate-level functional sim and was only caught by the formal check. The author also found the synth file named in the issue is not the one the layout was made from.