Build-A-Chip-Bench

Build-A-Chip-Bench evaluates AI agents on the full chip-design flow, from workload specification through GDS layout, using open-source tools and an open-source PDK. ChipAgents is developing it with contributions from NVIDIA to the benchmark suite and scoring rubric. Existing benchmarks test isolated steps such as writing RTL from a specification; this one spans all twelve major steps from workload and architecture through RTL, verification, synthesis, floorplan, placement, clock tree synthesis, routing, signoff and physical verification.

Each task runs in a sandboxed agent container with open-source tooling and an open-source PDK, on Nangate45 with OpenROAD. The agent receives a workload specification and a pinned interface. Verification lives in a separate hidden container with hidden test vectors and verification IP that the agent can query but not inspect, and a grader in a third container scores the final submission against a reference design that calibrates the task constraints.

Each design must pass a hard gate covering functional correctness against the hidden verification IP as well as routability, hold timing and DRC, and designs that pass are scored on PPA against the task constraints. The page reports the best agent passing the hard gate on 65 percent of tasks and reaching an overall score of 16.6 percent. The example task builds a Qwen3-0.6B INT4 inference accelerator to GDS at 400 MHz on Nangate45.