ChipVerilog

ChipVerilog is a description-to-Verilog generation benchmark built from OpenCores IP and core designs, addressing the gap that most existing benchmarks use short, self-contained module-level tasks that do not capture the code scale, hierarchy and module interactions of practical IP and processor-core RTL.

The benchmark contains 64 generation targets from five design families: OR1200, double-precision FPU, MIPS-16, I2C and CORDIC. It includes both single-module targets and cross-module targets that instantiate or interact with other RTL modules, and several targets exceed 1,000 lines of Verilog, making it substantially larger and structurally more complex than typical module-level suites.

Each benchmark instance is constructed from a pair of specification documents and reference RTL. The authors extract the target functionality, write a detailed natural-language description and manually review it for correctness and clarity. Generated RTL is checked by compilation and validated through equivalence checking for local modules, or by simulation for integrated IP and core targets. Results show large-scale RTL remains challenging, especially for hierarchical and cross-module designs.