veriflow-rtl-benchmark

VeriFlow RTL Benchmark is an open test kit for checking whether AI-written Verilog RTL actually works. It is an independent harness for scoring RTL that a pipeline like VeriFlow-CC produces, and it is not VeriFlow-CC and contains none of its code. Five small designs, each with a frozen written spec: a 4-deep 8-bit FIFO, a simple UART transmit and receive, an AXI-lite register block, a CORDIC rotation unit, and a small cache controller.

Every generated design is checked four ways: golden-model equivalence (a Python reference model run cycle by cycle against the RTL in simulation, which is bounded checking over test vectors, not a formal proof), lint (the RTL must compile cleanly with Icarus Verilog), synthesis (the RTL must synthesize with Yosys), and retries, tokens and time taken from each run's metadata when the generator reports them. Requirements are Python 3.10 or later with iverilog and yosys on PATH; no Python packages are needed.

First live results dated 2026-10-12: Codex CLI (gpt-6.1-sol, medium reasoning) using VeriFlow-CC's four-stage method passed 15 of 15 runs (5 designs by 3 runs) on golden-model equivalence, lint and synthesis. The harness was inspected against upstream VeriFlow-CC revision 77eca651d0e6ec93ed5309060980c54e76af7432.