tsci check netlist and plain tsci check print "Errors: 1" for a floating must-connect pin and exit with code 0. tsci build on the same file exits 1. So any script or CI job, or any agent loop that reads the exit code, treats a broken netlist as clean.
Recurring agent failure issue in cli (tscircuit)
What engineers report
A recurring agent failure problem in cli (tscircuit) that mostly hits the electrical engineer.
Failure pattern: agent / false pass
Analyst note
From the Grok pain-radar digests, Nov 11-12 2026 (Nov 11 8:41 AM ET through Nov 12 5:41 AM ET digests plus the Haitch editions). Verified live 2026-11-12: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to cli (tscircuit).
Evidence
More recurring errors in cli (tscircuit)
- Gerber via tenting landed in circuit-json-to-gerber 0.0.122 and the runframe updater picked it up, but the CLI stayed locked on 0.0.120, and a fresh install of the already-built CLI cannot replace its embedded converter, so published CLI ZIP exports still miss the bottom mask opening on a via that should be top-tented and bottom-exposed.ECAD · impact 74
- Importing CAP1188 succeeds even when the datasheet metadata lookup returns 404, and the generated part names the exposed pad pin25 with no ground requirement although the datasheet says it is GND.ECAD · impact 74
- The CLI bundles circuit-json-to-kicad 0.0.257, so KiCad ZIP exports drop an authored min_board_edge_clearance even though the fix shipped upstream, and KiCad falls back to its 0.50 mm default; on a real NEMA34 reduction, native KiCad 10.0.5 reports 4 copper-edge errors before and 0 after, with byte-identical PCB files. Second hour in a row the tscircuit CLI lock held back a published fix.ECAD · impact 74
- The CLI's KiCad project export used a hardcoded stub .kicad_pro, so explicit board limits (min trace width, copper-to-edge clearance, via pad and hole sizes, netclass track width) did not make it into the KiCad file, even though a different code path in the same repo already exported them correctly.ECAD · impact 74
- 'tsci export -f glb' cannot load a component STEP model given by relative path (404), but 'tsci build --glbs' loads the same file. Export still writes a GLB, just without the model: 21 KB vs 63 KB. Anyone handing that GLB to an enclosure person gets a board missing parts and no error.ECAD · impact 66
- `tsci check netlist` printed 'R1 (1kOhm undefined)' and listed resistor pins as anode and cathode, so the netlist people read to check a design was wrong about what is on the board.ECAD · impact 66
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.