A PCB flow found KiCad's 0.25 mm copper-to-hole default silently standing in for the fab's value, and a hand-made stackup draft with stripline widths off by about 10%. The generated 6-layer stripline widths are 0.1841, 0.1616 and 0.1177 mm against a hand draft of 0.165, 0.1484 and 0.1085, and the fab's minimum via left a ring thinner than its own floor.
Recurring agent failure issue in hive-pcb-flow (Hive-RSI-Lab)
What engineers report
A recurring agent failure problem in hive-pcb-flow (Hive-RSI-Lab) that mostly hits the electrical engineer.
Failure pattern: validation / silent failure
Analyst note
From the Grok pain-radar digests, Nov 10-11 2026 (Nov 10 8:41 AM ET through Nov 11 7:41 AM ET digests plus the Haitch editions). Verified live 2026-11-11: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to hive-pcb-flow (Hive-RSI-Lab).
Evidence
More recurring errors in hive-pcb-flow (Hive-RSI-Lab)
- An agent PCB flow cannot instance one schematic sheet N times, so repeated channels get copied by hand and drift. On a hifi receiver the left and right amps were generated as separate files with their own ref ranges: only 25 of 44 parts pair up by ref suffix, 8 of those pairs have different footprints, and 17 and 19 parts have no counterpart at all.ECAD · impact 74
- A KiCad point release turned a clean USB-C footprint into four DRC errors with no way to waive them. Fixtures recorded clean on 10.0.3 fail on 10.0.6: hole clearance on J1 is 0.18 mm on GND and 0.21 mm on VBUS against a 0.25 mm default.ECAD · impact 66
- A schematic library writes every hierarchical label as an input, whatever it was told, and KiCad lists multi-unit parts in page order, so netlist compares break after a redraw. Found on a board with dual op-amps and split MCU symbols: each placed unit was measured as the whole symbol, so bodies and pin bands were overstated.ECAD · impact 66
- An agent PCB flow moved lessons out of one team's private notes into the files its agents read. Board setup ignores the project footprint library table, a scratch copy loses custom design rules on refill, hand-added parts drift on the LCSC field and leave a stale position CSV, a USB-C connector has 0.1 mm pad polygon gaps, and one 50/60-pin connector symbol clashes.ECAD · impact 66
- An unlisted 48 V net defaults to 0 V in the creepage check. A code survey found more silent passes after an earlier fix covered 15 checks: rails with no known voltage only count the pin, current, thermal and return-path checks go quiet when their constraints block is empty, and unknown connectors skip the keying rule.ECAD · impact 66
- Board lessons that never made it into docs, recorded so agents can use them. EasyEDA footprints for 12.5 mm electrolytic cans with a courtyard round the leads only (7 x 2 mm), two pulled SOIC-16W footprints with lands 7.1 mm and 8.08 mm apart, a board library named 'power' shadowing KiCad's power symbols, and DFN die pads on copper with no paste or mask.ECAD · impact 66
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.