On a hierarchical project, create_board_from_schematic failed with '__bool__ should return bool, returned str' whenever a child sheet had exactly one hierarchical label, which is common for a small sheet that exports one signal. The parsing library returns a bare element for one item and a collection for two. Schematic to board sync broke on an ordinary design pattern.
Recurring agent failure issue in KiCAD-MCP-Server (mixelpixx)
What engineers report
A recurring agent failure problem in KiCAD-MCP-Server (mixelpixx) that mostly hits the electrical engineer.
Failure pattern: agent / failure
Analyst note
From the Grok pain-radar digests, Nov 11-12 2026 (Nov 11 8:41 AM ET through Nov 12 5:41 AM ET digests plus the Haitch editions). Verified live 2026-11-12: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to KiCAD-MCP-Server (mixelpixx).
Evidence
More recurring errors in KiCAD-MCP-Server (mixelpixx)
- A .kicad_dru file that does not parse is ignored as a whole with DRC exit 0 and no rule violations, of two matching rules the later one wins even when it is looser, a rule on an undefined net class matches nothing with no report, and kicad-cli 10.0.8 DRC segfaults with no report on a creepage rule when the board has no Edge.Cuts outline. On a high-voltage board, DRC passed can mean DRC ran no rules.ECAD · impact 74
- An audit of all 247 MCP tools found names lying in both directions: tools that look read-only or export-only rewrite the design by default, including lint_schematic_cosmetic rewriting the schematic, export_dsn writing net classes into the board, and hierarchical_place saving the board.ECAD · impact 74
- If the schematic is open in KiCad 10 while the AI edits it, KiCad never notices the file changed, and the next save in KiCad silently wipes the AI's edits, while the board side has a guard and schematics do not.ECAD · impact 74
- KiCad can change a via's net when it saves a board, and nothing reports it. DRC does not flag it. A via placed inside another net's zone took that zone's net, and after an autorouter SES import, a GND via came back on ISENSE_ADC and two VBAT vias came back as GND. The team caught it only by comparing the board via by via with the previous commit, which is now a permanent step in their checklist. On an 800 V board, a via silently moved from a low-voltage net to a high-voltage one is a safety problem.ECAD · impact 74
- The MCP sync tool built its pad-to-net map with its own geometric walker instead of asking KiCad, split nets that change name at a sheet boundary, missed labels in the middle of a wire, flattened names, and left new footprints with no symbol path. On a real 77-part, 9-sheet board, 304 of 333 pads were wrong while the tool reported success, with 349 parity issues. The fix reads KiCad's own netlist and gets 0 of 333.ECAD · impact 74
- The modify_trace command reported success and the change vanished on reload. The tool changed width, layer and net on the in-memory board but was never on the list of commands that trigger auto-save, so the change existed only in that in-memory board, discarded on the next project load. It also skipped the live IPC path, so a KiCad window open on the board did not show the change until a revert or restart. Same bug shape as an earlier add_layer issue.ECAD · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.