A cover module's mounting hole is meant to screw into an enclosure boss past the board edge, and the tool has no way to say so. Every hole row is treated as a site on the board. A site past the outline is a defect for both the grader and the placer, so place_simple refuses the module with exit 4 and the cover reads not mountable. Neither the design brief nor mechanical.json has a key for an enclosure hole. The one workaround is to leave the hole out, and then nothing checks it.
Recurring agent failure issue in KiCadRoutingTools (drandyhaas)
What engineers report
A recurring agent failure problem in KiCadRoutingTools (drandyhaas) that mostly hits the electrical engineer.
Failure pattern: validation / failure
Analyst note
From the Grok pain-radar digests, Nov 11-12 2026 (Nov 11 8:41 AM ET through Nov 12 5:41 AM ET digests plus the Haitch editions). Verified live 2026-11-12: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to KiCadRoutingTools (drandyhaas).
Evidence
More recurring errors in KiCadRoutingTools (drandyhaas)
- A .kicad_dru rule says HV nets need 0.6 mm, but route.py prints it as handled, lists no unsupported rules, and ships HV copper 0.2 to 0.58 mm apart. With --clearance-ceiling 0.1 it also rewrites the .kicad_pro HV class to 0.1 mm, so kicad-cli DRC and check_drc both report a clean board.ECAD · impact 82
- A class-scoped disallow track layer rule is treated as consumed. route.py puts 11 HS tracks on B.Cu, check_drc says clean, board_score reports 0 blocking, while KiCad itself reports 11 items_not_allowed.ECAD · impact 82
- On the orbiter_kb board the final route step ships GND open, and only KiCad's refill catches it. The copper grading passed it. The tool's fill model counts a 106 mm2 B.Cu island as joined to the main flood, and KiCad does not, and the repair step cannot weld the link either, because kicad-cli anchors the zone end at an outline corner that sits off the board.ECAD · impact 82
- A routed board passes check_drc, board_score and check_complete after its floors are lowered, but the grade against the authored project reads UNSOUND, and KiCad finds about 170 clearance errors at the authored project.ECAD · impact 74
- A weld moved a track to 0.1304 mm from a foreign via against 0.2 mm clearance, and the sweep's gate only checks the net's own connectivity.ECAD · impact 74
- An escape via cut a guarded pour, two pads ended open and the gate accepted.ECAD · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.