With kpex held at 0.3.12 and KLayout moved from 0.30.3 to 0.30.10, the extracted current mirror's header went from 'vref vss vcopy sky130_gnd' to 'sky130_gnd vcopy vref vss'. Same port set, every device card byte-identical, stable across runs. The reporter ruled out KLayout's SPICE writer by measurement before filing. Filed Aug 10, active again today.
Recurring agent failure issue in klayout-pex (iic-jku)
What engineers report
A recurring agent failure problem in klayout-pex (iic-jku) that mostly hits the electrical engineer.
Failure pattern: validation / failure
Analyst note
From the Grok pain-radar digests, Nov 10-11 2026 (Nov 10 8:41 AM ET through Nov 11 7:41 AM ET digests plus the Haitch editions). Verified live 2026-11-11: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to klayout-pex (iic-jku).
Evidence
More recurring errors in klayout-pex (iic-jku)
- A KLayout-PEX run succeeded while a device dropped out of the extracted netlist, because the PEX and LVS decks had drifted apart and unrecognized device shapes extracted as plain wiring.Verification · impact 74
- Every defect in #211 section C finishes with exit 0 and gives a netlist that simulates to a plausible wrong number. What caught them was a set of independent checks run on the output after every extraction: every device terminal has to sit on its own net's resistor network, every net has to be one connected piece, no port can touch nothing, total capacitance per net pair has to match the tool's own summary, and device counts by class have to match the schematic.ECAD · impact 74
- KPEX extraction turns subcell pin labels into ports the top cell keeps internal. Child cells carry pin labels for their own LVS, and extraction promotes them to top-level ports on ordinary hierarchical analog macros. Labels that are right at one level of the hierarchy produce a wrong netlist at the next.ECAD · impact 66
- On IHP sg13g2, KPEX 2.5D errors out on PCell inductors and HBTs because the tech info does not model the inductor pin layer or emitter window and has no device mapping for inductors.Verification · impact 66
- The klayout-pex check step exits 1 on BAG and xschem schematics because its SPICE reader does not understand parameters or expressions.Verification · impact 66
- The kpex --check command on a sky130A netlist with units KLayout expects fails on correct devices and exits 1, while the same lines without units pass. Two tools in one flow read the same SPICE line at different scales: schematic MOSFET sizes in microns, KLayout in metres.ECAD · impact 66
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.