For chip layout extraction, the --pins option folds label names but ignores their order, so the subcircuit header follows layout label order. A layout labeled out, en, vss, vdd against a schematic header of en, out, vdd, vss trips pin_order_mismatch and the extracted leg never runs. The workaround is a hand-written wrapper subcircuit in the testbench.
Recurring agent failure issue in klayout-tools (2AMLogic)
What engineers report
A recurring agent failure problem in klayout-tools (2AMLogic) that mostly hits the electrical engineer.
Failure pattern: validation / failure
Analyst note
From the Grok pain-radar digests, Nov 10-11 2026 (Nov 10 8:41 AM ET through Nov 11 7:41 AM ET digests plus the Haitch editions). Verified live 2026-11-11: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to klayout-tools (2AMLogic).
Evidence
More recurring errors in klayout-tools (2AMLogic)
- A klt DRC report from a sky130 run records the PDK as gf180mcuA in its provenance block while the deck field in the same block says sky130, so any gate keyed on provenance.pdk would reject good sky130 evidence or accept it as gf180mcu.ECAD · impact 74
- A substrate-only LEF pin gets bound to whatever net sits at the centre of its box; on an 8.6k-instance sky130 block, 606 of 7901 instances landed on the wrong net, and LVS then reports 652 errors that describe the probe, not the layout.ECAD · impact 74
- Follow-up to the sg13cmos5l version-drift issue: an operator ruling that violations inside unmodified foundry cells are a disclosed exception, pinned to the cell's content hash and its rule counts.Verification · impact 74
- klt drc on a PDK-drawn nfet_10v0_asym reports clean while layers 210/0 and 226/0 show up under layers_in_stream_without_rules; the PDK ships 35 ldnmos and 38 ldpmos rule outputs and the curated deck has none of them, so a clean report says nothing about coverage.ECAD · impact 74
- The synthesis check re-hashes RTL and liberty but records no hash of the netlist it produced, so it cannot catch a committed gate-level netlist that was hand-edited or went stale after resynthesis. It also needs the PDK on the checking host, so signoff CI skips it.ECAD · impact 74
- Upstream klayout-tools issue behind sky130-trng #386, covering the extractor writing a device outside the model bins without warning.ECAD · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.