zoneflow (syntroniks) errors

4 recurring problems engineers report in zoneflow (syntroniks), ranked by impact.

#142 by errors trackedECAD

Recurring zoneflow (syntroniks) errors, by impact

  1. 1A second fail-safe review on zoneflow found a keep-alive pin next to GPIO37, which the design doc called unconnected, but on the N16R8 module it is the PSRAM data strobe. A bridge of up to about 5 kohm between them kept both detectors on during reset, and the merged self-test could not catch it. Another PR merged mid-review, so the schematic had to be redrawn to match the netlist pin for pin, and that same merge swapped C1 for a lower-ESR part, raising worst-case fault current to 49 to 52 A against a fuse rated to interrupt 50 A.ECAD · Agent failure · 1 report74
  2. 2An independent review of the rev A layout for an 8-zone controller found 30 issues: 1 blocking, 9 major. The blocking one was 26 of 307 placements wrong against JLCPCB's own library footprints (triacs, opto-triacs, USB ESD arrays, the module, connectors). The buck converter's exposed pad had no via, two clearances were not checked by DRC the way the document claimed, and a patch router ignored the keep-outs the autorouter respected. All of it sat under a passing build, and the verdict is still 'ready for a prototype order after the human checklist, and not before.'ECAD · Agent failure · 1 report74
  3. 3A reviewer who wrote none of the repo read all of it and found 10 major and 19 minor self-disagreements. The README said the PCB layout was unfinished when it was routed, DRC clean and reviewed, and the status page counted 27 bench risks while the register had 34. The one that matters for agents: CLAUDE.md told the agent to edit design/board.toml, but design/layout.py writes that file, so any edit was lost on the next make. Every pin, net and dimension still matched across hardware, firmware and enclosure; the drift was all in the text people and agents read first.ECAD · Agent failure · 1 report66
  4. 4zoneflow generates its schematic from a netlist YAML so the drawing cannot state a connection, and the capture script refuses any wire between pins of two different nets. Parity checks match 346 components and 198 nets, and both build variants' BOMs. Two builds of KiCad 10.0.8 wrote different bytes, with one netlist line with U7's unit ids reordered and every SVG plot reordered.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure4

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.