booley

Open-source agentic RTL IDE that turns Claude Code or Codex into a sandboxed developer agent with real EDA tools, typed end-to-end sim, lint, synth, and FPGA flows, and a goal mode that checks acceptance criteria in deterministic code.

AgentOpen sourceActiveVerificationEmbedded

What it does and how it connects

Booley is an open-source agentic development environment for FPGA and ASIC work: the user directs Claude Code or Codex agents while they do the RTL work. Each Developer Agent runs in a Docker sandbox, is handed real EDA tools, and has its work checked against acceptance criteria the user sets, such as passing tests, area and timing budgets, cycle counts and coverage.

Typed EDA flows replace per-repo glue Tcl scripts: sim, lint, synth and fpga each run an EDA job end to end and return a structured result with pass or fail plus metrics such as area, timing or cycle counts. Simulation and elaboration use Verilator and Icarus Verilog, lint uses Verilator and Verible, synthesis uses Yosys with OpenROAD for physical estimates, and FPGA implementation uses AMD Vivado, with Synopsys VCS and Cadence Xcelium listed as coming soon.

In Goal Mode the user sets mandatory goals up front, such as a synthesis area increase of at most 10 percent or line coverage of at least 90 percent, and Booley checks each one in deterministic code against fresh recorded flow results, not against the agent's claim of success. A bwave command lets the agent query real simulation traces, and sessions, RTL, terminals, EDA runs and waveforms sit side by side in one VS Code window. It runs on Windows and Linux; macOS is not supported.

What engineers report

  • Windows init cannot resolve an installed Booley launcher during interactive setup.

Sources

  1. 1READMEgithub.com
  2. 2GitHub repo statsapi.github.com
  3. 3Websitebooley.dev
  4. 4GitHub issue 313github.com

Not verified

  • Pricing: none stated on the repo or site.
  • Real user voices: voice taken from issue 313, the repo's only third-party issue; the other public issues are the maintainer's own work-tracking items.
  • No Verilog or Vivado error ids exist in the error map, so no related errors are recorded.

Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.