VLSIT_RTL_Generator_AI_Flow

VLSIT is an AI-assisted RTL design and verification workflow that organizes work from hardware specification through requirements, configuration, RTL, SVA assertions and testbench, verification and documentation. Claude Code slash commands and Codex CLI skills walk an agent through the phases, with a Requirement Traceability Matrix linking each requirement to its specification clause, reviewed SVA, test cases, DUT results and human sign-off.

RTL generation and verification generation are separate branches sharing an approved baseline: the verification branch builds SVA and testbenches from the approved verification contract without reading the RTL, and the flow gates on human review at requirements, contract, properties and final verification. The repository also ships a reusable RTL IP library, common_rtl, with FIFOs, AXI4, APB, AHB and TL-UL bridges, CRC variants and a HyperRAM controller, each with its own specification.

Tools used are Verilator for lint, Yosys for synthesis, and the installed simulator for SystemVerilog and SVA, on Linux with Claude Code or Codex CLI. The README states the analyzed snapshot has no LICENSE file and that use and distribution terms must be confirmed with the repository owner, so no license is recorded for this page. Saved design snapshots describe individual runs and do not replace reproducible regression, formal proof, STA or ASIC sign-off.