chipleap

ChipLeap takes a workload description, such as Llama 3.2 1B decoding at 5 tokens per second, with area, power and process limits, and designs the chip for it: it sizes the problem, explores architectures by trying every single change and keeping the best one, writes down why, then generates the hardware as accelerator RTL in SystemVerilog, an X-HEEP RISC-V SoC configuration or AXI4 IP for any host, plus a C driver, a testbench and a datasheet. Or the user brings RTL of their own and ChipLeap checks it down to the layout.

Verification runs lint, simulation against a golden model, coverage, formal checks, CDC checks, synthesis, equivalence and place and route, on open-source tools or the commercial ones the user already has. The open flow is Verilator, Icarus, slang, cocotb, Yosys and LibreLane (OpenROAD, KLayout, Netgen) on the IHP SG13G2 open PDK. The README's worked example, a hand-written UART with cocotb tests at 100 MHz on SG13G2, reports 221 cells, 0.0041 mm2, a 1.01 ns critical path, and DRC, LVS and antenna clean at signoff, with 0 DRC violations, LVS match and 0 antenna violations on the whole die.

An assistant gets the same checks through an MCP server and can fix RTL in a loop. With a chip section the project becomes a whole chip: the core, hardened blocks from macro packages and a pad ring of IHP IO cells, routed by LibreLane, with bond pads, a seal ring and fill, timed at its own ports through the pads and checked with the IHP DRC and LVS decks.