digital-chip-design-agents

digital-chip-design-agents is a Claude Code marketplace plugin for the full digital chip-design pipeline: 16 plugins, 17 skill files, 14 chip-design domains plus infrastructure and a pipeline orchestrator, with closed-loop verification to RTL feedback. It installs with one command (npx digital-chip-design-agents), with no clone and no Python, and Claude loads the correct skill when the user describes a task in natural language.

The domains are architecture evaluation, RTL design in SystemVerilog, functional verification with UVM, formal verification, logic synthesis, design for test (scan, ATPG, JTAG), static timing analysis, high-level synthesis, physical design from floorplan to sign-off, SoC IP integration, memory IP design, compiler toolchain, embedded firmware, FPGA emulation, infrastructure and memory, and pipeline orchestration. Each plugin installs a skill with domain knowledge and an orchestrator agent that manages the full multi-stage flow, enforces pass and fail criteria, applies loop-back rules when a stage fails, and escalates clearly when human input is needed.

Each domain orchestrator reads from and writes to a two-tier persistent memory store, and the 14 domains connect into a complete spec to tape-out pipeline. An optional companion, hdl-rtl-skill, adds a slang-backed per-write lint hook, golden RTL templates and an anti-pattern catalogue for Claude Code only.