PCBBench (schematic synthesis)

PCBSchemaGen is the code and data for a NeurIPS 2026 paper on reward-guided LLM code synthesis for PCB schematic design with structured verification. It ships two benchmark suites: PCBBench with 62 hand-authored tasks and Open-Schematics-Eval with 165 tasks drawn from public schematics, for 227 tasks in total, plus a knowledge-graph component library.

The model writes SKiDL code for a schematic, and a reference-free verifier scores the resulting netlist snapshot without any reference design. Before verification, generated code passes a syntax check and a sandboxed SKiDL execution with KiCad ERC. The verifier then applies layered checks: electrical invariants, power-electronics invariants, pin-role compatibility, subcategory templates, and topology signatures, with a piecewise reward from 0.0 for no code block to 1.0 when all checks pass.

The repository also ships a refinement loop that retries failed designs with Thompson sampling scheduling, prompt templates, and a board-calibration tool that converts the original Open-Schematics KiCad boards into verifier inputs. The benchmarks and knowledge graph are MIT licensed, while the framework code is PolyForm Noncommercial 1.0.0, for research, teaching, and other noncommercial purposes.