Phoenix-bench
511 verified Verilator instances across 114 hardware repos with Docker-pinned EDA toolchains and SWE-bench-style fail-to-pass testbenches.
What it does and how it connects
Phoenix-bench asks whether agentic AI systems built for software engineering transfer to realistic hardware engineering. Existing hardware LLM benchmarks isolate sub-tasks, but none jointly requires repository navigation, hierarchy-aware localization, EDA executable verification and maintenance-style patching. Phoenix-bench is a synchronized corpus of 511 verified Verilator instances from 114 GitHub repositories, each shipped with the developer patch, design-flow labels, fail-to-pass and pass-to-pass testbenches, and a Docker-pinned EDA environment so resolved-rate differences reflect agent behavior rather than toolchain availability.
The paper runs a uniform evaluation of four commercial agents and eight open-source agentic structures across four LLM backbones, plus two diagnostic interventions: file-level oracle localization and one round of testbench-log feedback. Three findings emerge. Software and hardware are fundamentally different engineering tasks: the same agent loses 37 to 58 percent from SWE-bench Verified to Phoenix-bench, because hardware bugs propagate across parallel instantiated modules through signal flow rather than along a software-style call graph.
Failures concentrate on design control-flow and finite state machine bugs, verification testbench bugs, and hard cases demanding cross-hierarchy signal-flow tracking and coordinated multi-file edits. Localization granularity matters more than localization itself: a perfect file-level oracle yields only plus 1.4 percent, while a single round of test-case feedback lifts resolved rate by 42 to 45 percent, because the test case tells the agent where the bug is and what the fix has to look like.
Alternatives
Compare side by side- HWE-Bench
417 real fail-to-pass bug-fix cases from six open-source hardware projects with a live leaderboard, rather than 511 Verilator instances across 114 repos.
- ChipBench
44 hierarchical Verilog modules, 89 injected-bug debug cases and 132 reference-model tasks, rather than 511 Verilator instances across 114 repos.
- CVDP
783 engineer-authored problems across 13 categories covering RTL design and verification, rather than 511 Verilator instances across 114 repos.
- RealBench
60 module-level and 4 system-level tasks from real IP, evaluated with Verilator plus JasperGold formal, rather than 511 Verilator instances across 114 repos.
- VerilogEval
156 HDLBits-derived description-to-Verilog tasks verified by Icarus Verilog simulation, rather than 511 Verilator instances across 114 repos.
Sources
Not verified
- License: no license is stated on the arXiv page read.
- A public repo or dataset link: no repository URL appears on the abstract page read.
- Pricing: none stated (research benchmark).
- Real user voices: no real linked post read for this page.
- Related Error Index entries: no matching entry verified.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.