HWE-Bench

417 real fail-to-pass bug-fix cases from six open-source hardware projects (ibex, cva6, caliptra, rocket-chip, XiangShan, OpenTitan) with a live leaderboard.

Eval / BenchmarkOpen sourceMaintainedECADVerification

What it does and how it connects

HWE-bench is a benchmark for evaluating coding agents on RTL and hardware bug-fixing tasks. It curates 417 real bug-fix cases from six open-source hardware projects (ibex, cva6, caliptra, rocket-chip, XiangShan and OpenTitan) across Verilog, SystemVerilog and Chisel. Each case is verified end-to-end via simulation fail-to-pass: the included test fails on the buggy commit and passes after the fix.

The evaluation runs through a Harbor-based harness with per-PR Docker images: generate task directories, run the agent, extract patches and score. A full run over all 417 cases typically takes around a day of wall-clock time with four concurrent containers. Generated tasks prohibit external access so agents cannot look up the upstream PR or patch during runs.

Results are published on an interactive leaderboard with overall and per-repository scores, file-level precision, estimated token-equivalent cost and scaffold filters. The README reports reference scores including GPT-5.5 xhigh at 79.4 percent and Claude Opus 4.7 max at 74.6 percent as of 2026-04-30. OpenTitan images are not distributed because that flow requires Synopsys VCS.

  • Phoenix-bench

    511 verified Verilator instances across 114 hardware repos with Docker-pinned EDA toolchains, rather than 417 fail-to-pass cases from six projects.

  • ChipBench

    44 hierarchical Verilog modules, 89 injected-bug debug cases and 132 reference-model tasks, rather than 417 fail-to-pass cases from six projects.

  • CVDP

    783 engineer-authored problems across 13 categories covering RTL design and verification, rather than 417 fail-to-pass cases from six projects.

  • RealBench

    60 module-level and 4 system-level tasks from real IP, evaluated with Verilator plus JasperGold formal, rather than 417 fail-to-pass cases from six projects.

  • TuRTLe

    A unified harness running VerilogEval, RTLLM, VGen, RTL-Repo and NotSoTiny under several simulators, rather than a bug-fix benchmark with per-PR Docker images.

Sources

  1. 1READMEgithub.com
  2. 2GitHub repo statsapi.github.com
  3. 3Leaderboardpku-liang.github.io

Not verified

  • Pricing: none stated on the repo (open source benchmark).
  • Real user voices: no real linked post read for this page.
  • No GitHub releases exist, so latest release fields are null.
  • Related Error Index entries: no matching entry verified.

Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.