OpenLane
Open source flow and infrastructure library that takes digital chip designs from RTL to GDSII using open source EDA tools such as OpenROAD and Yosys.
What it does and how it connects
OpenLane 2 is an infrastructure library for building digital ASIC implementation flows from RTL to GDSII, based on open-source and commercial EDA tools. The documentation describes it as the release of OpenLane for use beyond the OpenMPW and chipIgnite flows, and points to the chipfoundry/openlane2 repository as its home (the docs still link the old efabless/openlane2 path, which redirects).
It includes a reference flow, called Classic and in beta, built entirely with open-source EDA tools, and lets designers abstract the underlying tools and configure their behavior with a single configuration file. Flows can be extended or modified with Python scripts and utilities. The default flow supports all variants of the open-source SkyWater PDK and some variants of the open-source GlobalFoundries PDK.
The older OpenLane 1 flow lives in The OpenROAD Project repository; the stats on this page are for chipfoundry/openlane2, the OpenLane 2 home named in the documentation. The repository is Apache-2.0 licensed; its only GitHub release is the 2.0.0b16 prerelease dated 2023-12-19.
The latest release is 2.0.0b16, a prerelease dated 2023-12-19; there are no stable releases. The repo moved from efabless/openlane2 to chipfoundry/openlane2.
What engineers report
The flow crashes at the Odb.ApplyDEFTemplate step.
2026-05-17Read the original
Alternatives
Compare side by side- Yosys
Yosys is a framework for Verilog RTL synthesis that turns designs into gate-level netlists, while OpenLane 2 is the full flow from RTL to GDSII.
- Verilator
Verilator is an open-source Verilog and SystemVerilog simulator and linter that compiles designs into fast C++ or SystemC models.
- KLayout
KLayout is a layout viewer and editor for chip mask layouts in GDS and OASIS formats, rather than an RTL to GDSII flow.
- KiCad
KiCad is a free, open-source electronics design suite for schematics and PCBs, rather than a digital chip implementation flow.
Sources
Not verified
- Pricing: none stated on the docs or repo as read.
- Related Error Index entries: no entry with software OpenLane was verified.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.