Verilator
Open source Verilog and SystemVerilog simulator and linter that compiles designs into fast multithreaded C++ or SystemC models.
What it does and how it connects
Verilator is an open source Verilog and SystemVerilog simulator and linter that compiles designs into fast multithreaded C++ or SystemC models. It accepts Verilog and SystemVerilog including UVM, performs lint code-quality checks, and can generate JSON to front-end other tools.
It is invoked with parameters similar to GCC or Synopsys VCS, reads the Verilog code, performs lint checks, optionally inserts assertion and coverage points, and outputs single- or multithreaded C++ and header files. It can generate a simulator executable automatically, or users can write their own C++ or SystemC wrapper. The project states its models run over 10 times faster than standalone SystemC on a single thread and about 100 times faster than interpreted Verilog simulators.
Verilator is guided by the CHIPS Alliance and the Linux Foundation, is free software under LGPL-3.0 or the Perl Artistic License 2.0, and offers commercial support contracts. It publishes no GitHub releases, so release fields are null; the project notes it may not suit SDF annotation or mixed-signal simulation.
No GitHub releases exist, so latest release fields are null.
What engineers report
With the DFG optimizer enabled, Verilator 5.052 and 5.054 (releases), 5.053 devel and current master print a wrong value for a correct, lint-clean design.
2026-11-06Read the original
Alternatives
Compare side by side- Yosys
Yosys is a framework for Verilog RTL synthesis that turns designs into gate-level netlists, rather than a simulator and linter.
- OpenLane
OpenLane 2 is an infrastructure library for building digital ASIC implementation flows from RTL to GDSII, rather than a simulator.
- KLayout
KLayout is a layout viewer and editor for chip mask layouts in GDS and OASIS formats, rather than a Verilog simulator.
- ngspice
ngspice is the open-source SPICE simulator for analog, digital, and mixed-signal circuits, driven by netlists and the command line.
Sources
Not verified
- Pricing: none stated on the vendor site or repo as read.
- Related Error Index entries: no entry with software Verilator was verified.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.