OpenROAD
Open-source RTL-to-GDS ASIC flow: the unified application implementing synthesis, floorplanning, placement, clock-tree synthesis, routing and sign-off on open PDKs.
What it does and how it connects
OpenROAD is the unified application implementing an RTL-to-GDS flow: synthesis, floorplanning, placement, clock-tree synthesis, routing, finishing, and sign-off, ending in a GDSII final layout. It takes Verilog plus libraries and constraints, and offers flexible flow control through an API with Tcl and Python bindings.
The project states its mission as eliminating the barriers of cost, schedule risk and uncertainty in hardware design, and describes the flow as autonomous, no-human-in-loop, with a 24-hour turnaround from RTL to GDSII for rapid design exploration. It is used in research and commercial applications such as OpenROAD-flow-scripts and OpenLane, and its documentation is at openroad.readthedocs.io.
The repo is the application itself; the flow scripts and PDK handling live in sibling repositories. The README carries build, Coverity, documentation and CII best-practices badges, and points to the project site at theopenroadproject.org.
Alternatives
Compare side by side- klayout-tools
Standalone Python tools that let AI agents parse, analyze and manipulate chip layouts headless, rather than the unified RTL-to-GDS application.
- vibe-ic
A Claude Code plugin that drives a full IC flow from natural-language intent, rather than the RTL-to-GDS application itself.
- uhdm2rtlil
A Yosys SystemVerilog synthesis frontend that converts UHDM to RTLIL, rather than a full RTL-to-GDS flow.
- hls4ml
A package that compiles machine-learning models to HLS for FPGA deployment, rather than an RTL-to-GDS ASIC flow.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- On a chip process with backside power layers, the router counts layers two different ways in one function, so it can pull track spacing from a never-enabled layer and compute the wrong tile size with no error.Error Index
- Since a change merged Oct 24, detailed_route starts at iteration 3 when DRC markers exist, skipping iterations 0-2 that route nets with guides but no wires; in an ECO flow after repair_design or repair_antennas, ripped-up nets are never routed while the command "reports 0 violations and returns normally".Error Index
- With the synthesis path on, the block kept default DEF units of 100 instead of 1000, so the final GDS streamed every coordinate truncated to 10 nm on a 1 nm process, producing 24,714 DRC markers and an LVS mismatch of 66 nets and 625 instances while the database itself was correct.Error Index
- The IHP SG13G2 LVS deck last synced in June 2024 missed the PDK top-port check, so a design with routing cut behind an IO pin still printed netlists match.Error Index
Sources
Not verified
- Pricing: none stated on the repo; the application is free and open source.
- No independent user voice found: recent repo activity is contributor pull requests.
- No GitHub releases exist on this repo (releases/latest returns 404), so latest release fields are null.
- The 24-hour RTL-to-GDSII turnaround is the project's own stated aim, not an independently verified figure.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.