hls4ml

Machine learning on FPGAs using high-level synthesis: compiles neural networks to HLS for FPGA deployment.

ToolchainOpen sourceActiveECAD

What it does and how it connects

hls4ml is a package for machine-learning inference on FPGAs. It creates firmware implementations of machine-learning algorithms using high-level synthesis, translating models from traditional open-source machine-learning packages into HLS that can be configured for the use case. It is designed for ultra-low-latency inference on FPGAs.

Its roots are in high-energy physics, such as L1 trigger systems at the CERN Large Hadron Collider, and it has been adopted for control systems for quantum computing, feedback loops in nuclear fusion, low-power environmental monitoring on satellites, and biomedical signal processing such as arrhythmia classification. Supported backends stated in the README are Xilinx Vivado HLS, Vitis HLS, Intel HLS, Catapult HLS and Altera HLS IP Gen.

Install is pip install hls4ml, with an optional profiling extra. A converter turns a Keras model into an HLS project, and the project page and tutorials live at fastmachinelearning.org/hls4ml.

What engineers report

  • The current SNN support works per time step and supports only linear layers. We would like to add support so ppl can reproduce the paper's firmware and build from there via the standard hls4ml flow instead of our standalone generator.
  • OpenROAD

    An RTL-to-GDS ASIC flow for synthesis through sign-off, rather than a package that compiles neural networks to HLS for FPGA deployment.

  • vibe-ic

    A Claude Code plugin that drives a full IC flow from natural-language intent, rather than a package for ML inference on FPGAs.

  • silica-eda

    An MCP server that gives coding agents structured access to an RTL-to-bitstream toolchain, rather than a converter from ML models to HLS.

Sources

  1. 1READMEgithub.com
  2. 2Latest release v1.3.0github.com
  3. 3User issue 1605github.com

Not verified

  • Pricing: none stated on the repo.
  • No matching Error Index entry verified for this FPGA HLS tool, so related errors are empty.
  • The voice quote is lightly trimmed from the issue body; the original wording is at the linked issue.

Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.