vibe-ic
AI-native IC design with Claude: a Claude Code plugin bundling an MCP server, an IP catalog and a benchmark harness that takes natural-language intent through to verified silicon, with every capability gated by a deterministic checker.
What it does and how it connects
Vibe-IC is a Claude Code plugin and MCP server that bridges large language models to real open-source EDA tools, so designers can drive an entire IC flow from a one-paragraph intent through design documents, RTL, FPGA verification and tape-out sign-off in natural language. One install bundles and auto-registers the MCP server, the IP catalog and the benchmark harness.
Every capability is gated by a deterministic checker, with no fabrication and no hallucinated PASS, per the README. The bundled MCP-EDA server runs the open-source EDA tools (Yosys, OpenROAD, KLayout, Magic, ngspice, and others) inside a Docker container named vibeic-eda, with an enhanced fork image carrying gatekeeper-verified fixes. The repo also holds open-core IP submodules (serv, ibex, sha256, opentitan) and a benchmark harness with 9 canonical benchmark ICs and 7 open-benchmark evaluation sets.
Status is v1.40, described in the README as mature and benchmark-hardened. Releases are assigned by a gatekeeper script whose patch range is 0 to 99, so x.y.99 rolls over to x.(y+1).0.
Alternatives
Compare side by side- OpenROAD
The unified RTL-to-GDS application for synthesis through sign-off, rather than a Claude Code plugin that drives the flow in natural language.
- klayout-tools
Standalone Python tools that let AI agents parse, analyze and manipulate chip layouts headless, rather than a plugin covering the whole IC flow.
- silica-eda
An MCP server that gives coding agents structured access to an RTL-to-bitstream toolchain, rather than a Claude Code plugin bundling server, IP catalog and benchmark harness.
- uhdm2rtlil
A Yosys SystemVerilog synthesis frontend that converts UHDM to RTLIL, rather than a plugin covering the whole IC flow.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- On a chip process with backside power layers, the router counts layers two different ways in one function, so it can pull track spacing from a never-enabled layer and compute the wrong tile size with no error.Error Index
- A truncating size cast inside an operator expression in a concat member was sized at the uncast width, so upper concat members dropped off and produced a wrong netlist with no warning.Error Index
Sources
Not verified
- Pricing: none stated on the repo.
- No independent user voice found: recent repo activity is maintainer pull requests and maintainer-filed issues.
- Related errors are for the OpenROAD and Yosys engines Vibe-IC drives, since no Vibe-IC-specific error entry exists.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.