silica-eda
AI-native EDA environment: an MCP server that gives coding agents structured access to an open RTL-to-bitstream toolchain. The agent lints, simulates, proves, synthesizes, places and routes, programs a board and reads its UART, and gets parsed results back instead of raw logs.
What it does and how it connects
Silica is an MCP server that gives coding agents structured access to an EDA toolchain. The agent lints, simulates, formally proves, synthesizes, places and routes, programs a board, and reads its UART through MCP tools, and gets parsed results back (errors with file and line, timing per clock, utilization, inferred memories, counterexample traces) instead of raw logs. A doctor tool reports which EDA tools are installed and how to install the rest.
Silica drives tools the user installs: open-source tools, mostly from the OSS CAD Suite, and commercial ones (VCS, Questa, Xcelium, Vivado, and others) when they are on PATH. The README states the full flow has been run end to end on a Digilent Arty A7-100T with a PicoRV32 RISC-V SoC: Verilator, Verible and svlint for lint; Icarus and Verilator simulation with waveform and coverage; SymbiYosys formal prove, cover and bounded checks plus eqy equivalence; Yosys synth_xilinx; nextpnr-xilinx place and route at a 100 MHz target routed at 153 MHz; programming with openFPGALoader; and a serial check over UART.
The server also tells the agent the order to work in and the pitfalls to avoid, so the loop (run the simulation, read the failure, fix the RTL, re-run) closes without copy-paste. Mock-free operation needs the underlying tools installed; the README lists how well each supported tool is tested.
Alternatives
Compare side by side- OpenROAD
The unified RTL-to-GDS application for synthesis through sign-off, rather than an MCP server that orchestrates the toolchain for an agent.
- vibe-ic
A Claude Code plugin that drives a full IC flow from natural-language intent, rather than an MCP server that exposes the toolchain directly.
- rtl_buddy
A YAML-driven CLI for Verilog and SystemVerilog simulation, regression, synthesis and place-and-route, rather than an MCP server for coding agents.
- eda-agent
An MCP server that lets agents read and modify a live Altium Designer session, rather than one that drives an open RTL-to-bitstream toolchain.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- On a chip process with backside power layers, the router counts layers two different ways in one function, so it can pull track spacing from a never-enabled layer and compute the wrong tile size with no error.Error Index
- A truncating size cast inside an operator expression in a concat member was sized at the uncast width, so upper concat members dropped off and produced a wrong netlist with no warning.Error Index
Sources
Not verified
- Pricing: none stated on the repo.
- No independent user voice found: the repo has no public non-PR issues listed via the API.
- Related errors are for the OpenROAD and Yosys engines Silica drives, since no Silica-specific error entry exists.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.