rtl_buddy
Python CLI for Verilog and SystemVerilog RTL design and verification: drives simulation, randomized regressions, synthesis, place-and-route, power analysis, formal checks and waveform viewing from one YAML config, for humans, CI and AI agents.
What it does and how it connects
rtl_buddy is a Python CLI for Verilog and SystemVerilog RTL design and verification. It drives the tools a project already uses from YAML configuration, with one consistent interface for humans, CI and AI agents. It covers simulation and randomized regressions, filelist generation, synthesis, place-and-route, power analysis, formal property verification, mutation testing, waveform viewing, hierarchy rendering, AXI profiling, and spec traceability.
Commands include rb test and rb regression across Verilator, Icarus Verilog and VCS with new-seed, repeat and replay support, rb synth with Yosys and an OpenROAD alternative backend, rb pnr with the OpenROAD flow, rb fpv for formal checks, rb wave for waveform viewing, and rb tool-check. Filelists are generated from models.yaml, and elaboration runs through pyslang without building a simulator.
A tour on the docs site runs every command unchanged against the project template, with every table and image taken from that run's real output. The project is on PyPI as rtl_buddy, and its docs are at rtl-buddy.github.io/rtl_buddy.
What engineers report
A closure can end on a round with max-slew violators even though a repair round would have fixed them, because round selection and the stop rule look at timing only, and the electrical-repair round runs repair_design without timing repair.
2026-11-04Read the original
Alternatives
Compare side by side- lintcrux
An RTL lint dashboard that drives six open-source lint engines into one SARIF-backed triage surface, rather than a CLI that runs simulations, regressions, synthesis and place-and-route.
- silica-eda
An MCP server that gives coding agents structured access to an RTL-to-bitstream toolchain, rather than a YAML-driven CLI for humans, CI and agents.
- uhdm2rtlil
A Yosys SystemVerilog synthesis frontend that converts UHDM to RTLIL, rather than a CLI that orchestrates simulation, regression and synthesis.
Sources
Not verified
- Pricing: none stated on the repo.
- No matching Error Index entry verified for this RTL CLI, so related errors are empty.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.