Yosys

Framework for Verilog RTL synthesis that turns hardware designs into gate level netlists for ASIC cell libraries and FPGAs, and serves as a formal verification front end.

ToolchainOpen sourceMaintainedECAD

What it does and how it connects

Yosys is a framework for Verilog RTL synthesis that turns hardware designs into gate-level netlists for ASIC cell libraries and FPGAs, and serves as a formal verification front end. It has extensive Verilog-2005 support and a set of synthesis passes that can be combined with synthesis scripts or extended in C++.

It converts Verilog to BLIF, EDIF, BTOR, SMT-LIB, and simple RTL Verilog, maps to ASIC standard cell libraries in Liberty format and to Xilinx 7-Series and Lattice iCE40 and ECP5 FPGAs, and includes built-in formal methods for checking properties and equivalence. It also serves as the back end for formal tools such as sby for SMT-solver-based property checking and mcy for mutation coverage.

Yosys is free software licensed under the ISC license, and the latest release at research time is v0.70.

What engineers report

  • Since #6447 (fix for #6409), verific -import no longer connects the output ports of blackbox cell instances.
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  • ngspice

    ngspice is the open-source SPICE simulator for analog, digital, and mixed-signal circuits, driven by netlists and the command line.

Recurring errors it addresses

Error Index entries this tool is built to reduce or work around.

Sources

  1. 1Yosys homepageyosyshq.net
  2. 2YosysHQ/yosys READMEgithub.com
  3. 3Yosys release v0.70github.com
  4. 4User issue 6460github.com

Not verified

  • Pricing: none stated on the vendor site or repo as read.

Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.