balloon-fresh (felixfelix-bot) errors

25 recurring problems engineers report in balloon-fresh (felixfelix-bot), ranked by impact.

#12 by errors trackedECADMCAD

Recurring balloon-fresh (felixfelix-bot) errors, by impact

  1. 1A base-station board had 143 electrical errors. 74 came from a copper pour that was never refilled, and the shipped board was built from a superseded netlist: the ERC-gated netlist has 53 parts while the board had 44, with twelve missing including the whole MCU decoupling ring and three removed resistors still on it. A netlist integrity test already failed on master and nobody acted on it, and refilling the 44-part board would have produced a board that looked clean while missing those caps.ECAD · Agent failure · 1 report74
  2. 2A dead boot pin was invisible in every count the project published. /IO0 was a single-pad net because the netlist was grown by text transform, and a one-pad net cannot be reported as unconnected. A renamed copy of the board silently lost its .kicad_dru rules and reported 537 violations instead of 16, and a sibling commit reported 15 to 12 from a work copy with a different baseline while the board of record went from 11 to 12. Four more nets have the same defect with no free GPIOs to fix them.ECAD · Agent failure · 1 report74
  3. 3An agent working on a fabricated hub board traced 3 failing connectivity tests to the tests and tools, not the board. The test and the pin registry both pointed at a superseded board file that was never fabricated, which produced 18 phantom 'pin absent' and 18 phantom 'not on board' drifts. One real drift remained: a commit changed U1.27 on the board without updating the registry. Worse, the suite had never run in CI, because the CI job did not install KiCad and 8 of 10 tests skipped quietly.ECAD · Agent failure · 1 report74
  4. 4Both CPL generators used KiCad's footprint anchor, which sits on pad 1 for pin headers, instead of the pad-array centre, so J_HUB_PV was 5.080 mm off and J_PROG 6.350 mm off and JLCPCB would have placed them where the pins cannot enter the holes. The existing check claimed verification to <0.001 mm, converted to JLC coordinates and back to the same anchor value, and the two generators also disagreed on board size, 72.10 x 80.10 vs 72.00 x 80.00.ECAD · Agent failure · 1 report74
  5. 5Every one of 14 pads referenced F.Mask but the board had none, so the export gave 9 files and zero mask gerbers, with SS24 diodes on 1.6 x 1.9 mm lands next to the cell string. Regenerating the file silently reduced the board from 32 track segments to 7, and the fix was to restore from git and patch the layer table directly.ECAD · Agent failure · 1 report74
  6. 6kicad-cli DRC 0 was unreachable by construction because 16 two-face wing pads and 3 GND zone stitcher records were counted as opens. A release gate that can never pass becomes a formality people learn to override, so exclusions are now derived from board geometry instead of a hand-written list.ECAD · Agent failure · 1 report74
  7. 7The balloon-fresh base station had a Python netlist generator as its only source of truth, so three merged repairs (regulator pinout fix, fixed 5 V TPS62163 change, RP2040 pin map) stayed logical-only because there was no schematic and no ERC. The new schematic is generated from the generator by parsing it, so it cannot drift, with parity 40 nets to 40 and 53 parts to 53. The board is untouched: 44 footprints, 0 tracks, 63 unconnected, 143 violations.ECAD · Agent failure · 1 report74
  8. 8The board declared copper, silk, edge and courtyard layers only, so kicad-cli silently skipped mask and paste gerbers and DRC reported 0 violations and 0 unconnected. Re-running the board generator also dropped the router's added segments, taking DRC from 0/0 to 6 unconnected.ECAD · Agent failure · 1 report74
  9. 9The docs said U_C was DNP, but the board file had DNP, exclude-from-BOM and exclude-from-pos all false, so following the docs JLCPCB would have soldered a LoRa module the BOM says is absent. The order sheet said top side, economic PCBA, all placements are top, while 4 of 23 placements are bottom side, and ordering single-sided would have returned ten boards with dead solar inputs.ECAD · Agent failure · 1 report74
  10. 10The double-sided JLCPCB upload zip on master still had J_HUB_PV 5.080 mm and J_PROG 6.350 mm off their holes, and U1 0.620 mm off, while the source CSV inside it was already correct. The top-only bundle was rebuilt and the double-sided one, the variant actually being ordered, was not.ECAD · Agent failure · 1 report74
  11. 11The fab package on master was built from board bda8d701, then the board moved twice, an /IO0 netlist change and U_C set DNP, with no regeneration, and copper happened to be identical, which the author calls luck, not process. The earlier 15/15 layers byte-identical result kept being quoted as current after the board changed twice underneath it.ECAD · Agent failure · 1 report74
  12. 12The only v10 gerbers sat in fab-11opens/, named for an 11-open board state, while the board of record had since been edited twice. The freshness script's first version had two bugs of its own: a dot vs underscore filename mismatch reported all 11 layers missing, and an integer regex on decimal coordinates parsed 0 drill hits on both sides and printed IDENTICAL. A third check compared BOM row count with CPL row count, which differ by design (14 grouped rows vs 23 placements).ECAD · Agent failure · 1 report74
  13. 13The readiness work was blocked on one question, which .kicad_pcb is the flight board. The answer is hub_board_v10_lora1280_7of9.kicad_pcb, not hub_board_v10.kicad_pcb, which still carries the old U_E28 radio with 730 track segments and 52 vias against 843 and 41. In the author's words, "quoting one board's DRC numbers for the other is invalid." Fresh native runs show 40 DRC violations and 86 unconnected. Schematic-to-board parity has 7 failures, including six nets on U_E28 in the schematic vs U_LORA1280 on the board. The part registry check says DRIFT 4, MISSING 52, "still E28-era.ECAD · Agent failure · 1 report74
  14. 14The route_batch.py script routed /IO0 twice and reported agreement_ok both times, while both routes shorted /IO0 to /USB_DN on B.Cu at the same spot. Its check compared its own A* grid to its own validator and never compared two nets, so it could not see a short. kicad-cli DRC caught it. Companion PR #489 found the /IO0 net had only one pad because the netlist was grown by text transform rather than from a schematic, and PR #490 found /EN cannot be escaped at all given the module's pad geometry. The fix runs kicad-cli DRC after every single net and rejects anything that adds a fatal violation.ECAD · Agent failure · 1 report74
  15. 15Three agents packaged the same board independently within an hour, and the board declared F.Mask and B.Mask on layer ids 9 and 11, which KiCad reserves for adhesive layers. All three variants still produced mask gerbers, which is why the wrong ids survived, and two design records still say 44 x 20 mm and 0.79 g per wing against a measured 34.60 x 20.00 mm and 0.62 g.ECAD · Agent failure · 1 report74
  16. 16A hole-to-zone clearance gate flagged 40 violations that did not exist, so CI on master could not go green. The custom check compared each drilled hole with each zone's bounding box; the pours cover the whole 71.1 x 79.1 mm outline, so 8 holes times 5 zones gave 40 'verify keep-out' records, none real.ECAD · Agent failure · 1 report66
  17. 17A protocol says '1.05 bar' without saying gauge or absolute, and that one word picks the pump: absolute means a 3.7 kPa rise, which any blood-pressure-class pump handles, while gauge means 105 kPa, beyond a 60 kPa pump. The author refuses to resolve that by assumption because the project's own records say mixing up 0.31 mbar and 0.31 PSI overpressured balloons before. The same PR notes JLCPCB cannot place a pump at all, so it moves off the board to a 2-pin header.MCAD · Agent failure · 1 report66
  18. 18An automated routing run measured each copper pour step. The F.Cu GND pour cut opens from 58 to 35 but left 6 pads on a single thermal spoke, where the baseline had none. A /+3V3 pour fixed 10 of its own opens and broke 22 GND connections. Neither shows up as a DRC violation, so a run judged by DRC count alone would have shipped a worse board.ECAD · Agent failure · 1 report66
  19. 19Freerouting's candidate routes caused collateral damage (opens went from 38 to 11 only after the team kept just the four good routes as templates); a gated router adoption check refused the full candidate on all four adoption checks before it reached the board, and schematic parity passed with 53 nets agreeing both ways.ECAD · Agent failure · 1 report66
  20. 20In balloon-fresh v11, the /SCAP_ADC net had two pads and no MCU pin, and no solar divider existed. The I2C bus had zero pull-ups while a decision record assumed it was ready. The v10 1 M / 1 M divider put 4.64 V on a pin rated 3.60 V absolute max.ECAD · Agent failure · 1 report66
  21. 21The author corrects an earlier claim that the pre-stretch board had no design, no schematic, no netlist. There is no PCB, but the firmware, the interlock module and its host tests define the hardware contract. From the fail-closed rule in interlock.h, they derive that the valve FET gate needs a pull-down, because the C3's pins float at reset. They also found the interlock is a STUB in main.c and the I2C bus runs at 100 kHz, not the 400 kHz they first assumed.ECAD · Agent failure · 1 report66
  22. 22The bot author opens with 'I was wrong, and the error has now been in three documents.' It had said D_BP3 had zero top-side sites and needed new copper, but it measured inside a 20 x 20 mm window around the part's v10 position while v11 is a re-layout, so the right search was the whole top face. Searched properly, D_BP3 has 194 sites and all four bypass diodes fit. A scoped measurement became a design fact and got copied forward before anyone checked the scope.ECAD · Agent failure · 1 report66
  23. 23The scraped price was the deep-bulk price. U1 C2980300 scraped at 3.722 but costs 5.8426 at qty 1, so a 5-board order understated the costliest part by 36 percent. Scraping the whole page also pulled ladders from alternative products. Real result: $52.36 per board at qty 1, $87.36 with hand-fit parts.ECAD · Agent failure · 1 report66
  24. 24The walkthrough told operators to expect 15 gerber files, but the real export is 28, so someone following the old text would have concluded their export was broken when it was correct. The drill check now lists all 196 holes by size, so a stale export is caught before upload rather than after payment.ECAD · Agent failure · 1 report66
  25. 25This PR adds a dual MS5611 pressure-sensor schematic, pinning CSB low to 0x77 for the internal sensor and high to 0x76 for ambient per the datasheet. The agent then notes RIG-ELECTRONICS-SPEC.md lines 114 to 116 reverse this polarity, but the doc is outside its edit scope, so the fix goes to a separate docs worker. The schematic and the spec now disagree on which address is which sensor.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure25

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.