hive-chip-flow
Chip-flow module: /vde, /ade and /msde chip-design skills and their engine, with hard-to-fool gates, and a release manifest tying every shipped file to its gate records.
What it does and how it connects
hive-chip-flow is the chip-flow module: ihsan-sa/chip-flow's chip design skills and their engine, packaged as a Hive module. An agent designs a chip block with open tools: /vde for a digital block in Verilog, /ade for an analog block, and /msde for a mixed-signal task that drives the other two.
Every result passes gates that are hard to fool (lint, simulation, formal proof, hardening, timing, DRC, LVS, SPICE at every corner, and planted faults each gate must catch) on its way to a GF180 Tiny Tapeout tile. The person signs off between stages, and submitting a tile is always the person's job.
A release manifest ties every shipped file to its gate records, and the score command reports the mean share of gate steps that passed a run on what each step reads now. The first blocks are an R-2R DAC and a PLL the Hive is designing.
Alternatives
Compare side by side- VLSIT_Q3TUI_AI_FLOW
A TUI and CLI taking a hardware IP block from intent to verified, synthesizable RTL through gated flows, rather than skills with hard-to-fool gates toward a Tiny Tapeout tile.
- eda-agent (MOREmbedded)
An MCP server for live Altium Designer sessions, rather than chip-design skills with gates toward a Tiny Tapeout tile.
- kicad-mcp-pro
An MCP server for KiCad workflows, rather than chip-design skills for Verilog, analog and mixed-signal blocks.
- universal-netlist
An MCP server that reads and queries schematics and netlists, rather than chip-design skills with gates.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- a racing telemetry board was reviewed against a local saved working board (PCB/schematic SHA256s pinned, not a pushed commit or fab release); ERC shows 0 but DRC shows 18 existing violations and 23 RF-only unconnected reports, and USB-only first flashing is still unqualified because USB powers the whole shared 3.3 V domain.Error Index
- 15 public Xyce regression decks run through ngspice and spice-ts: 12 failed in both engines, mostly on Xyce measurement syntax and dialect rejections, and all six AC decks failed; SPICE netlists still do not travel between simulators.Error Index
- Before pin-based LVS was added to AgentPIC, crossing waveguides passed every check: they merge into one region, so connectivity checks alone could not see them. The fix adds layout-versus-schematic checks re-extracted from coincident physical pins and an explicit no-crossing rule, plus a capability audit of what the agent can and cannot do.Error Index
Sources
Not verified
- Pricing (no price stated on the repository README)
- Real user voices (recent repo activity is the upstream author's own issues and pull requests)
- A named individual builder beyond the Hive-RSI-Lab organization
- A public release (no releases are published)
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.