hive-chip-flow's layout generator hardcoded device sizes, so a tuned sizing changed the schematic and never reached the layout. An optimiser winner updated one file and the GDS stayed the same. The generator now reads sizing.yaml and refuses sizes it cannot draw, and DRC, ERC, LVS and PEX records hash the sizing file.
Recurring agent failure issue in hive-chip-flow (Hive-RSI-Lab)
What engineers report
A recurring agent failure problem in hive-chip-flow (Hive-RSI-Lab) that mostly hits the electrical engineer.
Failure pattern: validation / failure
Analyst note
From the Grok pain-radar digests, Nov 10-11 2026 (Nov 10 8:41 AM ET through Nov 11 7:41 AM ET digests plus the Haitch editions). Verified live 2026-11-11: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to hive-chip-flow (Hive-RSI-Lab).
Evidence
More recurring errors in hive-chip-flow (Hive-RSI-Lab)
- A new logic-equivalence gate proving RTL equals the synth netlist equals the final netlist, run plainly, abstracts the clock with eqy, and on a small fixture it passed a wrong clock edge, a set flop in place of a reset flop, and a flop with no reset at all. A stray gate planted in the final netlist passed gate-level functional sim and was only caught by the formal check. The author also found the synth file named in the issue is not the one the layout was made from.Verification · impact 74
- A Tiny Tapeout tile shipped as custom_gds goes out with an empty gate-level netlist, and the shuttle own GL test cannot run because pdk.json carries no version. The local glsim gate runs on final/pnl, but nothing ties that netlist to the one in the submission.Verification · impact 74
- After an undeclared RTL edit, harden goes stale, but timing, DRC, LVS, glsim and precheck hash harden output, which has not changed yet, so the router and score report them fresh on a GDS that no longer derives from the RTL. The release step still refuses, but the freshness report undercounts what has to re-run.Verification · impact 74
- For a digital Tiny Tapeout tile, the GDS that gets taped out is not the one chip-flow signed off. The shuttle's GitHub action re-hardens with LibreLane 3.0.14 and tools at main, while chip-flow hardened with 3.1.0.dev3 and a pinned PDK, so timing, glsim, LVS and precheck all apply to a GDS nobody submits. The analog path avoids it only because someone committed the GDS by hand.Verification · impact 74
- On mixed-signal tops, the final LEF, SDF and SPEF are not in any gate input hashes. Swap the LEF after top_harden and release stages the new file and writes its hash into the manifest, and the ship check agrees because it compares against the same changed folder.Verification · impact 74
- Pinning the LibreLane version is not enough: the GitHub action cannot pin a PDK, and LibreLane fetches its own, gf180mcu f6eeac7, while signoff ran on open_pdks 1689ac3f. So a re-harden runs on a different PDK than the one that was signed off. The release now ships the signed-off GDS directly and refuses any workflow that would not reproduce signoff.Verification · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.