hive-chip-flow (Hive-RSI-Lab) errors

20 recurring problems engineers report in hive-chip-flow (Hive-RSI-Lab), ranked by impact.

#15 by errors trackedVerificationMCADECAD

Recurring hive-chip-flow (Hive-RSI-Lab) errors, by impact

  1. 1A new logic-equivalence gate proving RTL equals the synth netlist equals the final netlist, run plainly, abstracts the clock with eqy, and on a small fixture it passed a wrong clock edge, a set flop in place of a reset flop, and a flop with no reset at all. A stray gate planted in the final netlist passed gate-level functional sim and was only caught by the formal check. The author also found the synth file named in the issue is not the one the layout was made from.Verification · Agent failure · 1 report74
  2. 2A Tiny Tapeout tile shipped as custom_gds goes out with an empty gate-level netlist, and the shuttle own GL test cannot run because pdk.json carries no version. The local glsim gate runs on final/pnl, but nothing ties that netlist to the one in the submission.Verification · Agent failure · 1 report74
  3. 3After an undeclared RTL edit, harden goes stale, but timing, DRC, LVS, glsim and precheck hash harden output, which has not changed yet, so the router and score report them fresh on a GDS that no longer derives from the RTL. The release step still refuses, but the freshness report undercounts what has to re-run.Verification · Agent failure · 1 report74
  4. 4For a digital Tiny Tapeout tile, the GDS that gets taped out is not the one chip-flow signed off. The shuttle's GitHub action re-hardens with LibreLane 3.0.14 and tools at main, while chip-flow hardened with 3.1.0.dev3 and a pinned PDK, so timing, glsim, LVS and precheck all apply to a GDS nobody submits. The analog path avoids it only because someone committed the GDS by hand.Verification · Agent failure · 1 report74
  5. 5On mixed-signal tops, the final LEF, SDF and SPEF are not in any gate input hashes. Swap the LEF after top_harden and release stages the new file and writes its hash into the manifest, and the ship check agrees because it compares against the same changed folder.Verification · Agent failure · 1 report74
  6. 6Pinning the LibreLane version is not enough: the GitHub action cannot pin a PDK, and LibreLane fetches its own, gf180mcu f6eeac7, while signoff ran on open_pdks 1689ac3f. So a re-harden runs on a different PDK than the one that was signed off. The release now ships the signed-off GDS directly and refuses any workflow that would not reproduce signoff.Verification · Agent failure · 1 report74
  7. 7The clock-domain-crossing check assumes any undeclared input is synchronous. On a mixed-signal block, the analog side already says which outputs are asynchronous, but nothing carries that to the digital check, so an async comparator output sampled by one flop reads as clean.Verification · Agent failure · 1 report74
  8. 8The floating-net signoff gate reads a metric that LibreLane writes only at global placement, so anything that comes loose in CTS, resizing or routing is not counted. A probe on the final ODB found 9 unloaded nets, and OpenROAD own find_floating_nets did not reproduce the step count.Verification · Agent failure · 1 report74
  9. 9The mixed-signal gates do not hash every file they read, so an edit to a side spec, a pin map or analog sizing leaves a stale pass marked fresh. The project's own skill file says to re-run by hand, and both kinds of edit happened during the PLL bring-up.MCAD · Agent failure · 1 report74
  10. 10The recorded PLL top has 14 max-slew violations at the slow corner, yet top_harden passed, because slew and cap violation counts are not in the gate's metrics.ECAD · Agent failure · 1 report74
  11. 11The wrapper the flow generates leaves out the VGND and VDPWR ports that Tiny Tapeout analog template expects, and nothing refuses it. A correct hand-kept project.v gets refused as untied and only ships with a waiver, which has to be redone every time the file changes. The author diffed the two by hand and calls them equivalent by inspection, not by proof.Verification · Agent failure · 1 report74
  12. 12Antenna checks run nowhere for analog blocks: the block gate skips them, and the digital and top DRC skip them too, each assuming the other covers it. Nets inside the block are fully drawn, so their ratio is final and nobody checks it.Verification · Agent failure · 1 report66
  13. 13Gates now hash every file they actually open and pin the PDK version. The consequence is that every gate record made before this change cannot vouch for the PDK, so old passes read stale.Verification · Agent failure · 1 report66
  14. 14hive-chip-flow's layout generator hardcoded device sizes, so a tuned sizing changed the schematic and never reached the layout. An optimiser winner updated one file and the GDS stayed the same. The generator now reads sizing.yaml and refuses sizes it cannot draw, and DRC, ERC, LVS and PEX records hash the sizing file.ECAD · Agent failure · 1 report66
  15. 15Monte Carlo mismatch on a user subcircuit with m=4 still gets one unit mismatch, 3.94 mV against 2.22 mV for the equivalent single device. The mean is right and only sigma is wrong, so nothing looks broken. The script skips hierarchical m= on purpose and does not report that it did.Verification · Agent failure · 1 report66
  16. 16Setup and hold from the in-house cell characterisation are 1.9 to 4.2 times the shipped library values, which would show up as false setup violations in timing. min_pulse_width is not written at all because the search tool crashes.Verification · Agent failure · 1 report66
  17. 17The equivalence check matches state by name, so when yosys recodes an FSM a correct design fails, and the only way through is to turn recoding off.ECAD · Agent failure · 1 report66
  18. 18The independent timing re-check reads the signoff SDC with a bare read_sdc, while LibreLane propagates clocks when the SDC does not say. A block with its own SDC gets propagated clocks in LibreLane and ideal clocks in the second check, so the second signoff is the more optimistic one, with no skew at hold.Verification · Agent failure · 1 report66
  19. 19The staged Tiny Tapeout release shipped an empty .v with no verilog_path, and gate-level sim ran on the unpowered netlist while Lec and SDF read one netlist and the tile ships the other.ECAD · Agent failure · 1 report66
  20. 20The staged workflow has never actually run on GitHub Actions, so the PDK install, artifact paths, pinned precheck tools and YAML errors only Actions reports are all unverified before the first real submission.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure20

Engineering tools that address these errors

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.