NIATOLIP
Closed-loop PCB agent with gated component search and KiCad Docker workers for ERC, DRC and export.
What it does and how it connects
NIATOLIP (a working name; the public name is still to be found) is an agentic web tool for creating PCB boards: the user describes the board in natural language, an AI agent designs it, verifies it and corrects it in a loop, with live PCB, schematic and 3D preview, then exports the manufacturing files.
The validated stack is tscircuit with the Vercel AI SDK and the Meta Model API or OpenAI. The MVP scope is two-layer, low-speed boards (ESP32, RP2040, STM32) with components sourced from JLCPCB. Design and sourcing are decoupled in the V2 rework: part statuses run verified, out of stock, generic, custom or missing, and stock blocks only PCBA, never the design or the bare-PCB export.
KiCad is the final fabrication judge: the design exports to KiCad and kicad-cli runs ERC and DRC in a server-side Docker worker only, so the user installs neither KiCad nor Docker in hosted mode. The product documentation states the MVP was validated on 2026-10-29 and the V2 rework on 2026-10-30.
Alternatives
Compare side by side- tscircuit
The open-source toolchain NIATOLIP's design language is built on, for designing boards with TypeScript and React, rather than the agentic web tool around it.
- offgrid-hardhub
A description-to-board agent loop in real KiCad with about 90 board tests, rather than a tscircuit web agent with KiCad export.
- nia-tscript
A desktop PCB studio driven by an agent over MCP, by the same builder, rather than this web agent.
- kicad-mcp-pro
An MCP server exposing KiCad schematic, PCB, ERC/DRC, DFM, BOM and manufacturing export workflows, rather than a natural-language web agent.
- circuitron
An agent-driven PCB prototyper that turns natural-language requirements into SKiDL scripts and KiCad files, rather than a tscircuit web agent.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- An LLM-generated tscircuit design wrote holeDiameter on a hole element, a natural guess since platedhole and via use that prop name. The zod schema silently stripped the unknown key instead of rejecting it, leaving a null-diameter hole that turned into NaN bounds in the autorouter. Compilation reported 0 errors while the entire autoroute pass died for every net on the board; the crash only showed in stderr.Error Index
- The transistor component had a fixed pin order while common SOT-23 BJTs use a different order, and there was no way to remap because the schema stripped the pinLabels prop; a board could be built wrong without any error.Error Index
- An autorouting cache hit restored the traces but dropped the physical jumper components and pads: 3 jumpers and 24 pads cold versus 0 on the warm render.Error Index
- Crystals did not carry display frequency or load capacitance, so schematic labels needed special fallbacks and the BOM export dropped frequency entirely; the author also had to stop 32.768 kHz being rounded to 32.8 kHz.Error Index
- A KiCad MCP bridge normalizes DRC, connectivity, and geometry into its own output format, and that normalized output can silently disagree with the native KiCad engine. The maintainer had to build seeded false-PASS and false-FAIL tests because the bridge layer cannot be trusted as engineering truth on its own.Error Index
Sources
Not verified
- License (no LICENSE file in the repository and no license stated in the README)
- Pricing (no price stated on the repository README)
- Real user voices (recent repo activity is the maintainer's own issues)
- A named individual builder beyond the repository owner handle Marwichmisi
- A public release (no releases are published)
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.