On a real board the whole chain passed: check, cross-gate DRC, creepage, readiness READY, human sign-off, cart saved at JLCPCB. Then the owner opened the fab's gerber viewer and found the design unbuildable, with solder-mask openings missing and anchor holes in the wrong place. The tool records the human sign-off before the gerbers are even uploaded, so the name on the manifest vouched for a review that had not happened.
Recurring agent failure issue in kicad-tools (rjwalters)
What engineers report
A recurring agent failure problem in kicad-tools (rjwalters) that mostly hits the electrical engineer.
Failure pattern: agent / false pass
Analyst note
From the Grok pain-radar digests, Nov 11-12 2026 (Nov 11 8:41 AM ET through Nov 12 5:41 AM ET digests plus the Haitch editions). Verified live 2026-11-12: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to kicad-tools (rjwalters).
Evidence
More recurring errors in kicad-tools (rjwalters)
- A post-route pour-completion step adds GND and +3.3V vias and traces without ever reading the voltage map, with measured gaps including 0.400 mm where 1.60 mm was required next to a 150 V net, and the run ends with no warning.ECAD · impact 74
- A whole-board 'kct optimize-traces --drc-aware' pass on a freshly routed 4-layer JLCPCB board left 9 shorting items that kicad-cli DRC then found. The DRC-aware rollback was supposed to undo any merge that made DRC worse, and it did not catch them.ECAD · impact 74
- A wire-reinforced run (a bus wire soldered along an exposed trace) stands 1-2 mm off the board, but no check treats it as a physical object. On a real 4-layer mains board, 4 of 9 runs passed under same-side parts: a 5 W resistor body, three terminal blocks and the edge of two TO-220 courtyards. The tool's checks, KiCad DRC and the readiness gate all stayed green and said READY. A person found it in the fab's gerber viewer.ECAD · impact 74
- Analog (0.2 mm) and clock (0.25 mm) copper was routed first and preserved, then Signal nets (0.1016 mm) were routed around it. kicad-cli DRC finds 7 violations, for example SPI_SCK via 0.183 mm from an analog track that needs 0.2 mm, and NRST 0.224 mm from the oscillator pad that needs 0.25 mm. KiCad uses the larger of the two classes; the router used its own, and its post-route validation flagged none of them.ECAD · impact 74
- Board 03 seed 43 finished 25 of 27 nets with Manufacturable False while seed 42 finished 27 of 27; the 20 open links were GND and VCC pour links because the pour stage hit its deadline after 516.6 s of a 600 s budget, and the output looked the same as the closer tried and failed.ECAD · impact 74
- current-paths-audit (v0.25.0) marks a textbook Kelvin shunt tap (pad, short stub, via, sense IC pin) as ambiguous, while before the fix the INA181 taps joined force-bus copper 3 to 11 mm from the shunt, a real Kelvin error of roughly 10 to 30%, and the audit resolved all three paths through R9 without complaint; so the audit approved the broken board and flags the corrected one, and asks for a kelvin_taps spec field to declare intent.ECAD · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.