Ngspice cannot converge the loaded VCO above about 55 C, with twelve option variants all aborting at the first timepoint in the tail HBT model. The operator must choose between re-grading in Xyce, with results labeled as from a second simulator, and leaving 125 C ungraded as a recorded spec decision.
Recurring agent failure issue in sg13g2-lc-pll (2AMLogic)
What engineers report
A recurring agent failure problem in sg13g2-lc-pll (2AMLogic) that mostly hits the electrical engineer.
Failure pattern: agent / failure
Analyst note
From the Grok pain-radar digests, Nov 9-10 2026 (Nov 9 7:41 AM ET through Nov 10 7:41 AM ET digests plus the Haitch editions). Verified live 2026-11-10: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to sg13g2-lc-pll (2AMLogic).
Evidence
More recurring errors in sg13g2-lc-pll (2AMLogic)
- An open-PDK PLL run by an agent fleet. With the prescaler at 5.0 GHz, "FB and MC never toggle over 120 ns." Alone, the divider gives 3 FB edges at 500 MHz and 0 at 625 MHz, which is exactly the prescaler output. The existing divider bench "only counted at 100 MHz ('Not covered: speed'), so nothing caught this." Four spec rows can't close with the real chain, and the loop sim uses a behavioural stand-in. PR #65 adds the 625 and 687.5 MHz check and records the bisect but does not fix the divider. A verification record that honestly said "not covered" still let the design move forward.MCAD · impact 74
- An open-PDK PLL run by an agent fleet. With the prescaler at 5.0 GHz, "FB and MC never toggle over 120 ns." Alone, the divider gives 3 FB edges at 500 MHz and 0 at 625 MHz, which is exactly the prescaler output. The existing divider bench "only counted at 100 MHz ('Not covered: speed'), so nothing caught this." Four spec rows can't close with the real chain, and the loop sim uses a behavioural stand-in. PR #65 adds the 625 and 687.5 MHz check and records the bisect but does not fix the divider. A verification record that honestly said "not covered" still let the design move forward.MCAD · impact 74
- Chip design rather than boards, but the same mechanism. Divider speed decks use RF transistor models that need psp103_nqs.osdi, and the decks only load psp103.osdi. On a clean ngspice-46 host the run reports an unknown model type 4,208 times, the operating point fails, and three later simulations never run. The earlier passing record most likely relied on a host startup file that preloads the library. The author calls it unverified and a hidden host dependency either way. 23 comments in.Verification · impact 66
- The attested negative-control script targets two subcircuits that are gone from the netlist it reads, after a design decision replaced the first prescaler stage, and eight unused schematic and symbol files from before that decision are still in the tree. A check that silently tests nothing still reads as passing.ECAD · impact 66
- The prescaler's worst Vce exceeds BVCEO 2.2 V in 14 of 18 supply corners and four 125 C corners don't converge, so "the verdict cannot be a pass." The issue also asks whether 2.2 V is the right limit per device role, which is an EE question the bench can't answer.MCAD · impact 66
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.