sg13g2-lc-pll (2AMLogic) errors

6 recurring problems engineers report in sg13g2-lc-pll (2AMLogic), ranked by impact.

#80 by errors trackedMCADVerificationECAD

Recurring sg13g2-lc-pll (2AMLogic) errors, by impact

  1. 1An open-PDK PLL run by an agent fleet. With the prescaler at 5.0 GHz, "FB and MC never toggle over 120 ns." Alone, the divider gives 3 FB edges at 500 MHz and 0 at 625 MHz, which is exactly the prescaler output. The existing divider bench "only counted at 100 MHz ('Not covered: speed'), so nothing caught this." Four spec rows can't close with the real chain, and the loop sim uses a behavioural stand-in. PR #65 adds the 625 and 687.5 MHz check and records the bisect but does not fix the divider. A verification record that honestly said "not covered" still let the design move forward.MCAD · Agent failure · 1 report74
  2. 2An open-PDK PLL run by an agent fleet. With the prescaler at 5.0 GHz, "FB and MC never toggle over 120 ns." Alone, the divider gives 3 FB edges at 500 MHz and 0 at 625 MHz, which is exactly the prescaler output. The existing divider bench "only counted at 100 MHz ('Not covered: speed'), so nothing caught this." Four spec rows can't close with the real chain, and the loop sim uses a behavioural stand-in. PR #65 adds the 625 and 687.5 MHz check and records the bisect but does not fix the divider. A verification record that honestly said "not covered" still let the design move forward.MCAD · Agent failure · 1 report74
  3. 3Chip design rather than boards, but the same mechanism. Divider speed decks use RF transistor models that need psp103_nqs.osdi, and the decks only load psp103.osdi. On a clean ngspice-46 host the run reports an unknown model type 4,208 times, the operating point fails, and three later simulations never run. The earlier passing record most likely relied on a host startup file that preloads the library. The author calls it unverified and a hidden host dependency either way. 23 comments in.Verification · Agent failure · 1 report66
  4. 4Ngspice cannot converge the loaded VCO above about 55 C, with twelve option variants all aborting at the first timepoint in the tail HBT model. The operator must choose between re-grading in Xyce, with results labeled as from a second simulator, and leaving 125 C ungraded as a recorded spec decision.ECAD · Agent failure · 1 report66
  5. 5The attested negative-control script targets two subcircuits that are gone from the netlist it reads, after a design decision replaced the first prescaler stage, and eight unused schematic and symbol files from before that decision are still in the tree. A check that silently tests nothing still reads as passing.ECAD · Agent failure · 1 report66
  6. 6The prescaler's worst Vce exceeds BVCEO 2.2 V in 14 of 18 supply corners and four 125 C corners don't converge, so "the verdict cannot be a pass." The issue also asks whether 2.2 V is the right limit per device role, which is an EE question the bench can't answer.MCAD · Agent failure · 1 report66

How it fails

  1. Agent failure6

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.