edakit (tgd1975) errors

33 recurring problems engineers report in edakit (tgd1975), ranked by impact.

#8 by errors trackedMCADECADPLM

Recurring edakit (tgd1975) errors, by impact

  1. 1A bought USB-C breakout wired to the made board by cable is not in the design graph because every board in the graph has to be one edakit makes. Its missing CC resistors were found by another session after the order list was written, not by a check; with the breakout modelled, the check flags CC1 and CC2 as not connected.MCAD · Agent failure · 1 report74
  2. 2A gate run fails the hole check for U1 and D23 to D30. All nine have lead sizes in the parts database, keyed by manufacturer part number because they are bought at Berrybase, not LCSC, and edakit check, edakit sim and even pcb apply find those entries, but the fab release hole check looks parts up by LCSC code only, so it never sees them. The origin has no workaround.ECAD · Agent failure · 1 report74
  3. 3A project's stitching script adds vias and a pour to the PCB but can only run unregistered, by hand, and its step order lives as a note in CLAUDE.md rather than in the tool.ECAD · Agent failure · 1 report74
  4. 4After one rebuild the easyeda-mcp-pro bridge cannot verify, so it refuses every later rebuild until EasyEDA restarts, while edakit carried on with empty pours.ECAD · Agent failure · 1 report74
  5. 5An LED whose parts entry lacked a role the simulation reads was silently left out of the netlist, so earlier checks never saw it.ECAD · Agent failure · 1 report74
  6. 6Checked live on EasyEDA Pro 3.2.209 with easyeda-mcp-pro 1.8.0. The server's net listing takes parts and flags from every loaded page but wires from the focused page only, then joins them by coordinates. With the layout_tree page closed, pin U4.11 drops off the V_LED net again. The author first blamed EasyEDA, traced it to the bridge, and drafted an upstream issue and PR without posting them. The workaround stays in place. An agent reading this board gets a different netlist depending on which tab a human left open.ECAD · Agent failure · 1 report74
  7. 7EasyEDA rename calls look the item up in the left-panel project tree and answer false if that tree has not been shown since startup, so every rename failed until one manual click.ECAD · Agent failure · 1 report74
  8. 8EasyEDA reported 0 of 88 nets matching and the script saved the schematic anyway. An independent check about 10 minutes later showed 88 of 88, and the save step is still ungated.ECAD · Agent failure · 1 report74
  9. 9EasyEDA's Design Import Changes compares parts by Channel ID, but the API reads no Channel ID back from a schematic part, so the tool now writes the PCB's into the schematic itself, and without a PCB reload the second DRC still reported the fixed item.ECAD · Agent failure · 1 report74
  10. 10Gate --easyeda passed the schematic stage twice on Nov 1 and then failed it, with U4.11 on both U4_OUT6 and V_LED although the template has one wire at U4.11, and regenerating the template makes it pass again.ECAD · Agent failure · 1 report74
  11. 11The pour check measures the largest copper-free circle, so a long bare strip passes. EasyEDA drops any pour piece that touches no pad of its net, which leaves GND islands between header rows as bare stripes. Measured from released Gerbers rendered at 15.75 px/mm on five boards, one board passed with a 105 mm² bare piece along an Arduino Nano pin row.ECAD · Agent failure · 1 report74
  12. 12The silkscreen polarity check reported 8 signs correct and passed on a board with 33 signs. The front and back artwork boxes cover most of the board, and the check drops every sign inside an artwork's bounding box, so 25 signs were never judged. They were right, but only because the layout review measured all 25 by hand from the Gerber files.ECAD · Agent failure · 1 report74
  13. 13A pour rule fix built for one PR landed after it merged and sat on a branch with no PR, and it was not run on the five real boards because their Gerbers are build output.ECAD · Agent failure · 1 report66
  14. 14After a JLCPCB order, the maker confirms production files and parts placement, but the placement view opens in a second browser window the agent skill cannot see. The tool reads the renders against polarity sheets part by part and only signs off for the order's fab hash.ECAD · Agent failure · 1 report66
  15. 15All 206 tests pass, and none of them run the board and manufacturing-file checks; coverage on check_pcb, check_drills, check_copper, check_fab and the rest is zero lines, so green CI was telling them nothing about whether the release gate works.ECAD · Agent failure · 1 report66
  16. 16At JLCPCB a bare board goes straight from quote to cart, with no product description field and no upload named on the page. edakit cart check stopped both THT bell boards on the evening of Nov 1 because it expected the assembly form.PLM · Agent failure · 1 report66
  17. 17DRC ran against a PCB never reloaded since EasyEDA started, and a probe threw when the schematic tab was active, so DRC now reloads the PCB when it reports connection errors and runs once more.ECAD · Agent failure · 1 report66
  18. 18EasyEDA DRC cannot tell a pending import click from a real schematic or PCB mismatch: Netlist Error, Import Changes fails the release gate either way and only a count per kind is printed.ECAD · Agent failure · 1 report66
  19. 19EasyEDA stores no region name for NO_POURS keepouts, so edakit remembers region IDs in its own JSON file next to the board.ECAD · Agent failure · 1 report66
  20. 20easyeda-mcp-pro 1.7.0/1.8.0 shipped fixes that let them delete two local patch scripts. They still override the bridge timeout to 120 s because the default is 15 s, and still keep their own project-name check. Every project has to uninstall and reimport the bridge extension and restart EasyEDA. They won't merge before live checks in EasyEDA.ECAD · Agent failure · 1 report66
  21. 21Five Christmas-bell boards were released with JLCPCB as the only maker, and edakit refused quotes from other makers because their files and checks only appear after a new gate run.ECAD · Agent failure · 1 report66
  22. 22Found across nine EasyEDA sessions: once pads, vias or tracks are created or deleted through the API, the native copper-region rebuild returns no copper for every pour until the board is loaded again. A second pour run in one session failed, and the workaround is to save and reload before every fill.ECAD · Agent failure · 1 report66
  23. 23On a 40 x 40 mm board, edakit route all reported both GND pours ok, then no-copper on both, and said the bridge refuses every further fill until EasyEDA restarts. Saving, restarting and rerunning gave the same result twice, even though GND pads sit under both pours. What worked was manual: create pours, save, restart EasyEDA, then call the rebuild once per pour id in a set order, then put the tooling holes back.ECAD · Agent failure · 1 report66
  24. 24On a 40 x 40 mm LED board, the only GND pour went on the bottom, the top held pads and a few tracks, and edakit route all and the Gerber check reported nothing for TOP. Only the layout review caught it, and the author notes fixing it later costs a new order. The rule today only judges copper-free area on a face that has a pour.ECAD · Agent failure · 1 report66
  25. 25On a live EasyEDA run, "schematic check" matched, then the gate reported pin U4.11 on two nets, both reading the saved state. With another schematic tab closed the template matched, and opened again the second net came back. The fix closes every saved schematic tab before reading and names any open one with unsaved changes. An earlier fix had aimed at the wrong cause.ECAD · Agent failure · 1 report66
  26. 26On a single-sided board with five 0 ohm bridges, the checker raised two errors that are both false: a pull-up and the V_LED decoupling caps reach their nets only through the bridges, and the checker treats each bridge as a break; the simulator divides by the resistor value, so a 0 ohm part crashes it with ZeroDivisionError.ECAD · Agent failure · 1 report66
  27. 27Schematic create deletes and recreates the template, then stops on INVALID_TITLE_BLOCK_ITEM because EasyEDA now wants boolean showTitle/showValue and the tool sends None, leaving the template empty.ECAD · Agent failure · 1 report66
  28. 28The cart wrote a bare board's PCB fee using the estimate's size, which included the edge rails of its assembly class. Seen on a real order: estimated 85 x 66 mm, ordered bare, priced at 85 x 56 mm, and the fix reads the Gerber outline.ECAD · Agent failure · 1 report66
  29. 29The edge keep-out uses mitred joins, so at a notch it reaches d / sin(θ/2) into the board instead of the clearance d; on a real released routing that produced 100 "track in a keep-out" findings for tracks that keep the clearance, and Freerouting lost room in every notch because the same strips become its DSN keep-outs.ECAD · Agent failure · 1 report66
  30. 30The plan check uses part boxes that include silkscreen, so on an 84-part board it reports 19 overlaps; 17 are SMD pairs whose printed outlines touch by 0.03 to 0.44 mm while pads and bodies are well apart.ECAD · Agent failure · 1 report66
  31. 31The pour check passed with 595 mm2 of bare copper on the back in 29 spots, the largest 131.5 mm2, because channels between other nets' tracks belonged to no net's pour region.ECAD · Agent failure · 1 report66
  32. 32The tool's pour outline sits 0.55 mm from the board edge, but the order check demands 1.15 mm of copper clearance along tab zones, so the project does not run route pours on this board.ECAD · Agent failure · 1 report66
  33. 33Two 0805 parts tucked under an RP2350-Zero module on headers fail the plan check, and nothing in the config can say the module stands on headers; the origin design tool reports 0 findings for the same plan, so two tools look at the same board and disagree.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure33

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.