Silinx-ISE (pmnmalo) errors

5 recurring problems engineers report in Silinx-ISE (pmnmalo), ranked by impact.

#102 by errors trackedECADFirmware

Recurring Silinx-ISE (pmnmalo) errors, by impact

  1. 1A bus tap drawn the wrong way round turned a counter's 8-bit Q bus into a 1-bit wire, and the error blamed width mismatch and two drivers instead of the tap.ECAD · Agent failure · 1 report66
  2. 2A schematic bus tap on bits 5..5 of a 4-bit bus raises no diagnostic, while the generated HDL only warns, VHDL simulation stops, and Verilog gives x.ECAD · Agent failure · 1 report66
  3. 3Changing the project's preferred HDL from VHDL to Verilog saves the setting, but every schematic and state diagram keeps generating its old .vhd file.Firmware · Agent failure · 1 report66
  4. 4Without a PERIOD constraint on a DCM's pad, trce checks nothing, so a design can pass timing only because nobody told the tool what to check. Map and par also accept a DCM that trce later fails.ECAD · Agent failure · 1 report66
  5. 5Xilinx ISE 14.7 refuses escaped Verilog names in schematics, so the export wrote _opcode_0_, which ISE accepted but turned into an illegal VHDL port, and the import renamed it opcode_0, so the round trip cannot restore the original names.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure5

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.