openecos-projects/ecc
Open-source chip design automation solution: an RTL-to-GDS flow built on open source EDA tools.
What it does and how it connects
ECOS Chip Compiler (ECC) is an open-source chip design automation solution that integrates EDA tools (Yosys, ECC-DreamPlace, ECC-Tools, KLayout) to run a complete RTL-to-GDS design flow. It is developed and maintained by the ECOS Team. The GUI, ECOS Studio, has moved to a separate repository, so this repo is the command-line flow.
It is used two ways: as a project-oriented CLI (the ecc command) and as a Python API (the chipcompiler library). The recommended install is a shell installer for Linux x86_64, with an option to also install Yosys (OSS CAD Suite) and the ICS55 PDK, and nightly builds are available. Nix users clone with submodules and run it through the flake; building from source uses uv.
The installer wrapper lands in ~/.local/bin by default. The README links a development guide for the full source setup, and the project also ships Chinese documentation alongside the English README.
What engineers report
ecc diagnose run has inconsistent error handling for undeclared workspaces compared to other workspace-scoped commands in the same family.
2026-11-06Read the original
Alternatives
Compare side by side- tscircuit
A code-based PCB toolchain in TypeScript and React, rather than an RTL-to-GDS chip design flow.
- atopile
Describes boards in the atopile language and compiles them to KiCad, rather than running a chip RTL-to-GDS flow.
- tscircuit core
Builds Circuit JSON from TypeScript and React elements, rather than compiling RTL to GDS.
- circuit-json-to-kicad
Converts Circuit JSON into KiCad schematics and layouts, rather than running an RTL-to-GDS chip flow.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- An open chip flow ran Yosys on a 2.8 million cell design; the two gzip netlists the next steps read came out 20 bytes each and empty. Yosys exited 0, post-synthesis timing failed with "input contains no modules", and the flow still recorded Synthesis as Success.Error Index
- Clock tree synthesis aborted before it started when it read a full design SDC with set_case_analysis on test-mode pins, because the clock reader had no bound netlist yet, so the constraint could not resolve, found during the 2026-10 MPC order runs.Error Index
Sources
Not verified
- Pricing: none stated on the repo.
- A standalone vendor website: repo only.
- The ECOS Studio GUI: it moved to a separate repository and was not researched as its own page.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.