synth
Open source circuit compiler that lets engineers and AI agents describe boards in code and export KiCad files.
What it does and how it connects
Synth is an open-source compiler for electronic circuit boards. Engineers describe components, connections, and board constraints in SynthSpec, a text-based design language, and Synth checks the design and generates KiCad schematics, PCB layouts, and a bill of materials. The .synth files hold the design intent, so designs are edited in a normal editor and reviewed in Git.
Engineers drive it from the command line, and AI agents drive the same compiler through its Model Context Protocol server, which can retrieve the language reference, search for parts and their pin definitions, validate a design, apply fixes, and invoke placement, routing, and export. Prebuilt binaries ship for five platforms with a SHA-256 checksum beside each, and the project also installs from Git with Cargo.
Exported projects open in KiCad, and optional Gerber, drill, and STEP exports require kicad-cli. The vendor site frames the split as Community providing the open compiler while Enterprise adds a managed workflow and team support; no Enterprise price is stated on the site as read.
What engineers report
W-SYNTH-DRC-016 offers slow or one dielectric height. A 100 MHz SDR SDRAM bus on a 0.8 mm BGA cannot release.
2026-11-06Read the original
Alternatives
Compare side by side- atopile
A code-first language and compiler for electronics, rather than a SynthSpec compiler with an MCP server.
- tscircuit
Designs boards in TypeScript and React in a browser or CLI workflow, rather than compiling a text circuit language.
- KiCadAI
Generates KiCad projects deterministically from behavioral requirements with a pass or refuse gate, rather than compiling a text circuit description.
- pcbcraft
A Rust schematic and PCB editor built MCP first, rather than a compiler that turns text designs into KiCad files.
Recurring errors it addresses
Error Index entries this tool is built to reduce or work around.
- In a board generator, the router and project file use JLCPCB's 0.56 mm minimum via but the board setup hardcodes 0.60 mm, so kicad-cli DRC throws blocking errors on vias that are legal at the fab.Error Index
- FreeRouting finished its route, but the in-process KiCad stitch step got a bare SwigPyObject and crashed before DRC ever ran.Error Index
- The KiCad exporter placed a net label at a segment midpoint and silently merged RXD1_MCU into MODEM_IDLE, while the part registry gave two CH342F pins the same TNOW1 name.Error Index
- synth_export over MCP reported a board fabrication-ready with no missing footprints while the CLI refused the same board on part hdc1080_rh_t, whose WSON-6 footprint is not in the library, because the footprint check lived only in the CLI.Error Index
Sources
Not verified
- Pricing: none stated on the repo or the vendor site as read; the site names Community and Enterprise editions with no price.
- A named individual builder: the repository names the absmach organization, not a person.
Last verified November 6, 2026. Listings are informational. The evidence score measures public, verifiable evidence and is not an endorsement or a compatibility claim.