The verify gate missed an oasis erratum: a Q1/Q3 gate-source swap, which netlist_audit sot23_pinout would catch.
Recurring agent failure issue in hive-hwde (Hive-RSI-Lab)
What engineers report
A recurring agent failure problem in hive-hwde (Hive-RSI-Lab) that mostly hits the electrical engineer.
Failure pattern: validation / failure
Analyst note
From the Grok pain-radar digests, Nov 8-9 2026 (Nov 8 8:41 AM ET through Nov 9 6:41 AM ET digests plus the Haitch editions). Verified live 2026-11-09: issue/PR read; title and state confirmed.
What it costs a team
Modeled annual cost
$30,000
For a team of 5
Prototype delay
3 days
Modeled schedule slip per occurrence
Time lost
240 min
Per engineer per month, about 1 incidents
How the cost is modeled
240 min/month × 5 engineers × 12 months = 240 hours × $125/hour = $30,000
A modeled estimate with medium confidence. Swap in your own team size and loaded rate to size it for your team.
Engineering tools that address it
No engineering tool profile lists this error yet. Browse tools that connect to hive-hwde (Hive-RSI-Lab).
Evidence
More recurring errors in hive-hwde (Hive-RSI-Lab)
- A courtyard scoped clearance rule also covered pours crossing the courtyard, so check_creepage demoted a real thin pour to pad creepage error to a waived warning. A real creepage error passed as a waiver because the rule was scoped to the wrong object.ECAD · impact 74
- After importing an Altium board into KiCad, DRC ran on KiCad's defaults, 0.2 mm clearance and 0.5 mm to the edge. The author's 10 mil track and clearance, via sizes, mask rules and room-scoped rules were never read, so the board passed or failed against rules nobody wrote. The current workaround is a per-board fix_pcb.py script.ECAD · impact 74
- Altium, Allegro and PADS ship ODB++ or IPC-2581 next to Gerbers, and fabs like Eurocircuits, PCBWay and AISLER run CAM on that package directly. hive-hwde can export both, but its check_odb only checks that every reference designator is present, and nothing compares the package to the Gerbers, so a Gerber regenerated after a track move with a stale ODB++ would go out as two deliverables that disagree.ECAD · impact 74
- Board pads named A and C were not read as anode and cathode, so LED1 and power diode D2 fell back to the package table and came out reversed in the pick-and-place. A footprint origin away from the part centre only raised a warning, while the part would land off its pads at JLC by 2.81 mm on USB-C and 1.87 mm on Qwiic.ECAD · impact 74
- Boards that draw controlled-impedance copper as zones skip the checks: check_diffpair says coupling not evaluated, dfm_release reports min_trace_width_mm null. On zcoupon a pair zone was shaved to 0.1043 mm against a 0.127 mm fab floor, and DRC passed because the fill keeps clearance.ECAD · impact 74
- check_return_path demands a ground via within 2 mm of every high-speed layer change, and no router or tool places one. Freerouting adds none, the KRT GND-via option warned no GND net was found and is not wired to constraints, and stitching only does grids, so every inner-layer DDR/USB/PCIe transition on linux-computer, network-switch and zcoupon is born a return-path finding and fixed by hand.ECAD · impact 74
Sourced from public community reports. Costs and delays are modeled estimates, not measurements. Know a better source or a fix? Tell us at hello@productflo.io.