hive-hwde (Hive-RSI-Lab) errors

60 recurring problems engineers report in hive-hwde (Hive-RSI-Lab), ranked by impact.

#2 by errors trackedECADVerificationMCAD

Recurring hive-hwde (Hive-RSI-Lab) errors, by impact

  1. 1A courtyard scoped clearance rule also covered pours crossing the courtyard, so check_creepage demoted a real thin pour to pad creepage error to a waived warning. A real creepage error passed as a waiver because the rule was scoped to the wrong object.ECAD · Agent failure · 1 report74
  2. 2After importing an Altium board into KiCad, DRC ran on KiCad's defaults, 0.2 mm clearance and 0.5 mm to the edge. The author's 10 mil track and clearance, via sizes, mask rules and room-scoped rules were never read, so the board passed or failed against rules nobody wrote. The current workaround is a per-board fix_pcb.py script.ECAD · Agent failure · 1 report74
  3. 3Altium, Allegro and PADS ship ODB++ or IPC-2581 next to Gerbers, and fabs like Eurocircuits, PCBWay and AISLER run CAM on that package directly. hive-hwde can export both, but its check_odb only checks that every reference designator is present, and nothing compares the package to the Gerbers, so a Gerber regenerated after a track move with a stale ODB++ would go out as two deliverables that disagree.ECAD · Agent failure · 1 report74
  4. 4Board pads named A and C were not read as anode and cathode, so LED1 and power diode D2 fell back to the package table and came out reversed in the pick-and-place. A footprint origin away from the part centre only raised a warning, while the part would land off its pads at JLC by 2.81 mm on USB-C and 1.87 mm on Qwiic.ECAD · Agent failure · 1 report74
  5. 5Boards that draw controlled-impedance copper as zones skip the checks: check_diffpair says coupling not evaluated, dfm_release reports min_trace_width_mm null. On zcoupon a pair zone was shaved to 0.1043 mm against a 0.127 mm fab floor, and DRC passed because the fill keeps clearance.ECAD · Agent failure · 1 report74
  6. 6check_return_path demands a ground via within 2 mm of every high-speed layer change, and no router or tool places one. Freerouting adds none, the KRT GND-via option warned no GND net was found and is not wired to constraints, and stitching only does grids, so every inner-layer DDR/USB/PCIe transition on linux-computer, network-switch and zcoupon is born a return-path finding and fixed by hand.ECAD · Agent failure · 1 report74
  7. 7Fifteen checks now say when they judged zero items instead of reading as a pass, and one real miss surfaced: the annular ring check measured only outer layers, so a 0.083 mm ring on inner layers went unseen.ECAD · Agent failure · 1 report74
  8. 8Footprints pulled from EasyEDA for radial electrolytic caps came with a courtyard drawn round the pads only, while the 6.3 and 10 mm can is just a silk circle. The placement gate passed with an SO-8, 1210s and 0402s sitting physically under the cans. DRC only caught it later as silk_over_copper.ECAD · Agent failure · 1 report74
  9. 9Importing an Altium design, eda_io reports 18 of 23 parts as lost because the author renamed PCB designators to values (R1 shows as 1K5, C2 as 100n) and KiCad's importer takes the PCB text, not Altium's SOURCEDESIGNATOR. The Altium schematic cannot be compared at all because only an Eagle reader exists, so the import is counted, not compared.ECAD · Agent failure · 1 report74
  10. 10KiCad 10.0.6's Altium schematic importer embeds each symbol under its Altium library name and writes no symbol library or sym-lib-table. ERC then flags all 42 symbols, and the bare footprint names give 26 footprint link errors against the board import. Same board, same day, two imports that do not agree on where the parts live, and the workaround is another per-board script, fix_sch.py.ECAD · Agent failure · 1 report74
  11. 11KiCad's Gerber writer leaves corner arc ends up to 0.05 um off the straight edges, so the DFM step reads the outline as open and skips the edge checks. The joiner tolerance is 1e-5 mm and the arc error is 5e-5 mm, and right now a stand-in script snaps the outline.Verification · Agent failure · 1 report74
  12. 12Length matching counts copper pad to pad and ignores package pin delay, which KiCad, Allegro and Altium all read, so a DDR byte lane matched on the board alone is off by the package's own per-ball trace lengths. Two checks also count the via barrel differently, so a pair inside a length group gets measured as two different lengths.ECAD · Agent failure · 1 report74
  13. 13minuet v3's ESP32-C3 ROM pulls GPIO6 up at reset and powers the LED strip early. The check that would catch it (check_straps reset_pull_offboard) never runs on a board that arrives without a netlist or CPL beside it.ECAD · Agent failure · 1 report74
  14. 14mister1 placed 180 deg off in the JLC CPL. The check that would catch it (cpl_verify) never runs on a board that arrives without a netlist or CPL beside it.ECAD · Agent failure · 1 report74
  15. 15No check covers a raised model's standoff against the part's real height: minuet U1 is 17 mm against a 16 mm part.ECAD · Agent failure · 1 report74
  16. 16oasis v0.2 shipped with Rfbb1 as an 0402 part (C844504) on an 0603 footprint. The check that would catch it (check_bom_sync --live) never runs on a board that arrives without a netlist or CPL beside it.ECAD · Agent failure · 1 report74
  17. 17On a board with an aux origin, kicad-cli writes the IPC-D-356 netlist relative to that origin while Gerbers and drill files are absolute, giving 130 dfm_net_open errors and a shipped .ipc that would fail the fab electrical test. The same report found the DFM check splitting KiCad RoundRect pads into pieces, producing false 0.114 mm ring findings on pads whose real ring is 0.33 mm.ECAD · Agent failure · 1 report74
  18. 18On a LISN rev 2 board, eight inductors (Wurth 744325120, LCSC C1331072) have no EasyEDA model, so the placement check can never verify their rotation. "hwde gate" applies the DFM waiver and reports pass with 8 waived. "attest build" then reports 8 failing, because it only honours waivers from a different tool and a different file. The author says the refusal is the honest answer, since nobody has checked the rotation, and asks for either a hand-recorded fact with its own evidence, such as the rotation read from JLC's placement preview, or a gate that refuses waivers attest won't honour.ECAD · Agent failure · 1 report74
  19. 19On a mains PSU board, bulk sat on T1's dotted primary pin and D5's anode on the dotted secondary pin. That makes it a forward converter, so VDD heads to about 103 V against the controller's 38 V limit. "erc, verify, verify_release and attest build all passed. An independent cold review found it by reading the Würth drawing and TI's reference schematic pin by pin." The same review found the 12 V winding on the wrong pins (5 turns instead of 7). The ask is for transformer symbols to carry dots and a turns table, and for a check that compares wiring with the declared topology.ECAD · Agent failure · 1 report74
  20. 20On an Eagle board with a KiCad schematic, board_update lists 23 parts as unsupported pad_net_change, but every one is a rename: X1B vs /X1B, 0/TX0 vs 0{slash}TX0 from kicad-cli's escape, and N$9 vs Net-(J5-CC1). The ask is a rename mode when pad sets map one to one, as KiCad's Update PCB from Schematic does; the workaround is a board-local fix_pcb.py.ECAD · Agent failure · 1 report74
  21. 21On an i.MX6ULL board (0.8 mm pitch, 0.32 mm pads), via-in-pad escape routes 155 of 155 nets, then kicad-cli DRC rips 37. The fallback vias are held at the 0.45 mm fab floor so they bulge past the pads, the router's own stubs then pass 0.07 mm from them against a 0.125 mm rule, and they also hit decouplers on the bottom side. The rip leaves 150 to 170 dangling track stubs behind, and the router logged the problem and kept going.ECAD · Agent failure · 1 report74
  22. 22On the SparkFun Pro Micro RP2040, a board SparkFun has actually built, dfm_check fails 179 times, mostly against floors JLC does not publish: hwde holds a 0.45 mm minimum via diameter and 0.1 mm ring where JLC's page says 0.25 mm and 0.05 mm (0.45 mm is a cost tier, not a floor), 0.3 mm copper to edge where JLC says 0.2 mm, and one hole-to-hole rule where JLC has separate via, pad and castellated values. The ask is to keep preferred and min apart.ECAD · Agent failure · 1 report74
  23. 23Pin and ratings checks matched by number or name and raised four false suspects on one board, all of which turned out not to be defects against the datasheets. A check that joins the extraction pin 1 to the symbol pin 1 reads Vout on VCC on a mirrored PLR237 optical receiver even though the copper is right.ECAD · Agent failure · 1 report74
  24. 24Re-running intake with --force to bring in a fixed board wiped the whole workspace, including fw/, which was another agent's merged work, plus the import sources, the generators and the README. The files were recovered from git, and the ask is that --force only replace what intake wrote, or refuse when the folder holds files it did not make.MCAD · Agent failure · 1 report74
  25. 25Same board. CPL.csv gave U1 rotation 270, and the render showed its pins on the wrong sides. cpl_visual.json recorded "mismatch" for U1, "and reports/cpl_render.json still said pass, so a wrong placement rotation could reach a release unless someone reads the JSON." One 403 from EasyEDA also aborted the whole render. Two files in the same run disagreed, and the one people look at was the wrong one.ECAD · Agent failure · 1 report74
  26. 26The ESD coupling check reports open-circuit volts, about 5.8 V on a current-sense net next to USB D+, and cannot see the 10 ohm and 100 nF filter in front of the pin. The board pads have an empty pinfunction, so pin ratings cannot match from the board, while the netlist file does carry them.ECAD · Agent failure · 1 report74
  27. 27The isolation barrier check audits the gap after copper exists, but nothing upstream knows about it. The rules generator writes high-voltage DRC rules from creepage voltages and nothing from the isolation constraint, so routers and pours walk into the gap and the board finds out at final verify. One design keeps its 8 mm gaps with hand-placed keepouts in its own layout code. The ask is one source that DRC, routers and pours all read.ECAD · Agent failure · 1 report74
  28. 28The lab's JLC capabilities file sets a 4 mil clearance floor for 4-layer 2 oz boards. A reviewer read JLC's page the same day as 0.15 mm for 2 oz multilayer. The hc-power board had 249 different-net outer track pairs below 0.15 mm, down to about 0.12 mm, and both DRC and the DFM gate were clean. Every 2 oz multilayer row shares the same value, so other boards inherit the mistake. The workaround is a hand-added spacing rule in the board's .kicad_dru, and the author notes the rules generator would overwrite it. The annular ring figure on the same page is also unconfirmed.ECAD · Agent failure · 1 report74
  29. 29The new test-point check reports that on the hifi-receiver core 97 of 190 nets have no flying-probe access, +3V3A included, with 11.6% bottom-side fixture coverage and no test-point footprints at all, so bring-up probes rails by hand on 0402 toes (0.17 mm). The ask, with PR #556, is a step that places the missing test points and writes the ICT probe list for the fixture house, the way Allegro Testprep and Valor do.ECAD · Agent failure · 1 report74
  30. 30The schematic generator cannot instance one channel sheet N times, so each channel gets copied into its own file, and the copies drift. On a hi-fi receiver, the left and right amps pair only 25 of 44 parts, 8 of those pairs have different footprints, and 17 plus 19 parts have no counterpart. The board import also drops each part's sheet path, so KiCad's own repeat-layout tool cannot match them either.ECAD · Agent failure · 1 report74
  31. 31The SI simulator and check do not know which end of a net drives it, since EasyEDA-pulled symbols are all passive, so every pair runs four orientations and keeps the worst, reading 581 mV of noise against 331 mV with the real driver.ECAD · Agent failure · 1 report74
  32. 32The tool now proves which pin meets which across a cable between boards, but it does not check whether the cable can carry the current. A 0.5 mm FFC conductor is rated about 0.4 to 0.5 A, and nothing compares the rail's current per pin against that, adds cable IR drop (the board sims stop at the board edge), or checks FFC thickness and contact plating against the socket, so a cable can be ordered that does not hold.ECAD · Agent failure · 1 report74
  33. 33The verify gate missed a digits erratum: MIC_GND is floating, and the netlist_audit ground_island check that would catch it never ran.ECAD · Agent failure · 1 report74
  34. 34The verify gate missed an oasis erratum: a Q1/Q3 gate-source swap, which netlist_audit sot23_pinout would catch.ECAD · Agent failure · 1 report74
  35. 35200 open checker findings were judged one by one against board files and datasheets: 172 real, 28 false. On the core board 128 were real and 23 false, and the false ones turned into five new checker bugs, including a check that charges a plane whole budget to leaf stubs.ECAD · Agent failure · 1 report66
  36. 36A 0201 land with reduced paste has two unnumbered paste-only pads. cpl_verify counted them as pads, so every bottom-side 0201 failed as "more than two pads" and the DFM gate blocked 19 of 22 parts. Fixed with a new test case. Last hour this repo's gate passed things it shouldn't. This hour it blocked things it should have passed.ECAD · Agent failure · 1 report66
  37. 37Any FLEX_ rule area makes every via and PTH on the board need a teardrop, including ones deep in the rigid ends, and SMD pads on flex are not checked at all. Which vias count as flex is only a naming convention until there is a real declaration of the region.ECAD · Agent failure · 1 report66
  38. 38Changing a power plane region and re-running the plane generator added a new zone and kept the old one, leaving two +1V35_DDR and two +3V3 zones, zone-intersect DRC errors, and copper poured in the stale region. Removed by hand.ECAD · Agent failure · 1 report66
  39. 39dfm_check held a board on an HDI build to JLC's standard-build floors until this fix. Annular ring is now measured only on layers a hole actually crosses. In #618, escape routing for 0.4 and 0.5 mm BGAs on microvia stacks passed kicad-cli DRC with 0 errors, but both PRs say the whole suite wasn't run, and hdi-bga still hits open dfm_check items. Checks are only as good as the fab rules they're told to use.ECAD · Agent failure · 1 report66
  40. 40dfm_check held a board on an HDI build to JLC's standard-build floors until this fix. Annular ring is now measured only on layers a hole actually crosses. In #618, escape routing for 0.4 and 0.5 mm BGAs on microvia stacks passed kicad-cli DRC with 0 errors, but both PRs say the whole suite wasn't run, and hdi-bga still hits open dfm_check items. Checks are only as good as the fab rules they're told to use.ECAD · Agent failure · 1 report66
  41. 41DRC rules, pours and the auto-router did not share the isolation numbers the isolation check judges with, so rules_gen now writes barrier rules from the same table, though three routing steps still know only net-wide clearances.ECAD · Agent failure · 1 report66
  42. 42Eagle draws exposed-pad paste on a separate layer and turns the pad own paste off. KiCad importer brings those windows in as graphics, the paste check only read pads, and it reported missing paste. Once fixed, it found a real problem on a SparkFun board, with 18% paste coverage and windows sitting on 4 of 8 open GND vias.ECAD · Agent failure · 1 report66
  43. 43Frames and logos have schematic symbols but no pads, so ODB++ has no part record for them and the export reported them as lost. Same family as the parts lost on import findings from earlier today.ECAD · Agent failure · 1 report66
  44. 44Now that strap checks say mcu_unknown, it is visible how little they cover: the reset table has ESP32 rows and one RP2040 row, while STM32, ATmega and other boards judged nothing.ECAD · Agent failure · 1 report66
  45. 45On an Eagle schematic imported into KiCad, the pin-type tool turns power symbols and PWR_FLAG into passive, which breaks ERC's rail model, and leaves the RP2040's supply pins passive. Eagle types pins as io, so imports need the tool, and it does not work on them yet; the workaround is a board-local fix_sch.py.ECAD · Agent failure · 1 report66
  46. 46On an HDI BGA board, Freerouting sessions imported back into KiCad come in with "every non-through via buried." A new retype step took check_vias from 14 errors to 0. Best routing result still left 38 of 64 unrouted, and the end-to-end flow wasn't tested on a board that finishes.ECAD · Agent failure · 1 report66
  47. 47SparkFun 0402 layout, built and DRC clean at IPC least courtyards, cannot pass this placement gate, which grows each pad field by 0.25 mm. Logos, silk labels and castellations were also judged as placed parts. The house rule and the source design were written against different assumptions.ECAD · Agent failure · 1 report66
  48. 48The board EM solver writes lossless S-parameters on purpose, and nothing puts the loss back, so every Touchstone file overstates S21 and every downstream check (passivity, eye diagram, measured vs predicted) inherits it. On 100 mm of FR4 at 6 GHz that is about 1 to 2 dB missing, and the stackup parser also ignores KiCad's loss_tangent while the stackup table keeps tan d only as text.ECAD · Agent failure · 1 report66
  49. 49The DFM netlist compare did not read KiCad jumper pad groups, so every internally bridged pad showed as an open, even though KiCad DRC already counts them as connected. Once it read the same footprint data KiCad does, the fpga-adc board DFM gate went from 4 errors to a pass with 5 warnings.ECAD · Agent failure · 1 report66
  50. 50The diff-pair check treats a 'sense' pair as a DC Kelvin pair, but the rules generator gave the same declaration impedance width and gap rules, which DRC then failed.ECAD · Agent failure · 1 report66
  51. 51The fab export now ships an IPC-D-356 netlist, and DFM compares the shipped Gerbers against it for shorts and opens. On the first run, KiCad's zero-length slot drills for a USB-C connector read as 4 false opens, and the two formats had to be reconciled before the check meant anything.ECAD · Agent failure · 1 report66
  52. 52The quote tool priced Economic PCBA for a castellated board, and JLC own capability page says Economic does not support castellated holes. It also left out the via option the board vias force, and counted 48 parts where BOM and CPL have 42 because copper features and artwork got counted as placed. Found in a cold review, after the quote.ECAD · Agent failure · 1 report66
  53. 53The verify gate missed a minuet erratum: the U2 comparator input sits at about 3.1 V against a 2.6 V common-mode limit, which netlist_audit input_common_mode would catch.ECAD · Agent failure · 1 report66
  54. 54The verify gate missed a minuet erratum: U5 is missing its FB_BK 1 uF, which netlist_audit pin_part_missing would catch.ECAD · Agent failure · 1 report66
  55. 55The verify gate missed an oasis erratum: J1 power-input holes too big, and check_connector_fit tht_hole_loose cannot judge it without the part's mechanical data.ECAD · Agent failure · 1 report66
  56. 56The via stub check only measures vias. Plated through-hole pins on fast nets leave the same open barrel and are skipped. Back-drill clearance to other nets is not checked, no fab page found publishes a back-drill tolerance, and the EM cross-check never ran because the heavy queue did not reach it.ECAD · Agent failure · 1 report66
  57. 57Thirteen check areas (creepage, ratings, SI, current, thermal, return path, mate pins, diffpair, vias, cap load, wicking, testpoints, DFM) passed silently without judging anything, per #601.ECAD · Agent failure · 1 report66
  58. 58Three open-hardware boards pinned with 14 published errata; the gate caught 2 (digits J1 mirrored header, J7 labels) and missed 12.ECAD · Agent failure · 1 report66
  59. 59Tolerance analysis varies only passive initial tolerances at 25 C, while a real worst-case analysis also needs temperature, aging and active-part spreads like op-amp offset and regulator Vref. The board sim computes feedback and filter corners but never compares them to a constraint window.ECAD · Agent failure · 1 report66
  60. 60Two false losses on the same Altium crossover board: the export check called 59 parts lost from the ODB++, but all were board-only items like the frame, logos and silk labels, and with PR #562 the model path check flagged all 8 embedded 3D models as unanchored and failed verification, though the models travel inside the board.ECAD · Agent failure · 1 report66

How it fails

  1. Agent failure60

Sourced from public community reports. Costs and delays on individual entries are modeled estimates, not measurements.